公开(公告)号：US10148416B2

公开(公告)日：2018-12-04

申请号：US15255564

申请日：2016-09-02

Applicant: Intel Corporation

Inventor： Tonia G Morris ,  Ying Zhou ,  John V. Lovelace ,  Alberto David Perez Guevara

IPC: H04L7/00 ,  G11C7/00 ,  G11C29/02 ,  H04L7/033

Abstract: Embodiments are generally directed to signal phase optimization in memory interface training. An embodiment of an apparatus includes an interface for at least one signal; and interface training logic capable of automatically adjusting a phase relationship between the signal and a strobe or clock, including establishing a phase delay of the signal and a phase delay of the strobe or clock for training of the interface, wherein the interface training logic is capable of determining a phase delay reduction for the signal subsequent to measurement of an eye margin for the signal, the phase delay reduction to retain a sufficient delay to maintain the eye margin for sampling of the signal.

公开(公告)号：US09852021B2

公开(公告)日：2017-12-26

申请号：US14967226

申请日：2015-12-11

Applicant: INTEL CORPORATION

Inventor： Bill Nale ,  John V. Lovelace ,  Murugasamy M. Nachimuthu ,  Tuan M. Quach

IPC: G06F12/00 ,  G06F11/07 ,  G11C29/02 ,  G06F12/0813 ,  G06F13/16 ,  G06F3/06 ,  G06F12/0802 ,  G06F12/02 ,  G06F13/42 ,  G11C7/22 ,  G11C11/406 ,  G11C5/14 ,  H04L9/08 ,  G11C5/04 ,  G11C7/10

CPC classification number: G06F11/0793 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0638 ,  G06F3/0673 ,  G06F3/0683 ,  G06F11/0727 ,  G06F11/0751 ,  G06F11/0772 ,  G06F11/079 ,  G06F12/023 ,  G06F12/0802 ,  G06F12/0813 ,  G06F13/1663 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4234 ,  G06F13/4243 ,  G06F13/4282 ,  G06F2212/1044 ,  G06F2212/2532 ,  G06F2212/60 ,  G11C5/04 ,  G11C5/148 ,  G11C7/1003 ,  G11C7/1063 ,  G11C7/1072 ,  G11C7/222 ,  G11C11/40618 ,  G11C29/023 ,  G11C29/028 ,  H04L9/0869

Abstract: Provided are a method and apparatus for method and apparatus for encoding registers in a memory module. A mode register command is sent to the memory module over a bus, initialization of the memory module before the bus to the memory module is trained for bus operations, to program one of a plurality of mode registers in the memory module, wherein the mode register command indicates one of the mode registers and includes data for the indicated mode register.

公开(公告)号：US09627029B2

公开(公告)日：2017-04-18

申请号：US14639025

申请日：2015-03-04

Applicant: INTEL CORPORATION

Inventor： Tonia G. Morris ,  Jonathan C. Jasper ,  John V. Lovelace ,  Benjamin T. Tyson

IPC: G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G06F13/16 ,  G11C7/10

CPC classification number: G11C11/4076 ,  G06F13/1689 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/22 ,  G11C11/4096 ,  G11C2207/2254

Abstract: A memory controller transmits a control signal to a memory module, where the memory controller continuously transmits a clock signal to the memory module. The memory controller determines adjustments to the control signal with respect to the clock signal, by iteratively analyzing a strobe signal.

公开(公告)号：US09330734B2

公开(公告)日：2016-05-03

申请号：US14072540

申请日：2013-11-05

Applicant: Intel Corporation

Inventor： Christopher P. Mozak ,  Kevin B. Moore ,  John V. Lovelace ,  Theodore Z. Schoenborn ,  Bryan L. Spry ,  Christopher E. Yunker

IPC: G11C5/14 ,  G11C11/4074

CPC classification number: G11C11/4091 ,  G11C5/147 ,  G11C11/4074 ,  G11C11/4093 ,  G11C11/4099

Abstract: Described herein is an apparatus for dynamically adjusting a voltage reference level for optimizing an I/O system to achieve a certain performance metric. The apparatus comprises: a voltage reference generator to generate a voltage reference; and a dynamic voltage reference control unit, coupled with the voltage reference generator, to dynamically adjust a level of the voltage reference in response to an event. The apparatus is used to perform the method comprising: generating a voltage reference for an input/output (I/O) system; determining a worst case voltage level of the voltage reference; dynamically adjusting, via a dynamic voltage reference control unit, the voltage reference level based on determining the worst case voltage level; and computing a center of an asymmetrical eye based on the dynamically adjusted voltage reference level.