公开(公告)号：US20240105452A1

公开(公告)日：2024-03-28

申请号：US17952695

申请日：2022-09-26

Applicant: Intel Corporation

Inventor： Reza Bayati ,  Matthew J. Prince ,  Alison V. Davis ,  Chun C. Kuo ,  Andrew Arnold ,  Ramy Ghostine ,  Li Huey Tan

IPC: H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L21/28123 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: Techniques are provided to form semiconductor devices that include one or more gate cuts having a layer of polymer material at edges of the gate cut. The polymer layer may be provided as a byproduct of the etching process used to form the gate cut recess through the gate structure, and can protect any exposed portions of the source or drain regions from certain subsequent processes. The gate structure may be interrupted between two transistors with a gate cut that extends through an entire thickness of the gate structure and includes a dielectric material to electrically isolate the portions of the gate structure on either side of the gate cut. The edges of the gate cut may be lined with a polymer layer that is also on any exposed portions of the source or drain regions that were exposed during the etching process used to form the gate cut recess.

公开(公告)号：US20240113105A1

公开(公告)日：2024-04-04

申请号：US17937212

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Alison V. Davis ,  Bern Youngblood ,  Reza Bayati ,  Swapnadip Ghosh ,  Matthew J. Prince ,  Jeffrey Miles Tan

IPC: H01L27/088 ,  H01L21/762 ,  H01L23/522 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L27/088 ,  H01L21/76229 ,  H01L23/5226 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696

Abstract: Techniques are provided herein to form semiconductor devices that include gate cuts with different widths (e.g., at least a 1.5× difference in width) but substantially the same height (e.g., less than 5 nm difference in height). A given gate structure extending over one or more semiconductor regions may be interrupted with any number of gate cuts that each extend through an entire thickness of the gate structure. According to some embodiments, gate cuts of a similar first width are formed via a first etching process while gate cuts of a similar second width that is greater than the first width are formed via a second etching process that is different from the first etching process. Using different etch processes for gate cuts of different widths maintains a similar height for the gate cuts of different widths.

公开(公告)号：US20240105453A1

公开(公告)日：2024-03-28

申请号：US17953873

申请日：2022-09-27

Applicant: Intel Corporation

Inventor： Reza Bayati ,  Matthew J. Prince ,  Alison V. Davis ,  Ramy Ghostine ,  Piyush M. Sinha ,  Oleg Golonzka ,  Swapnadip Ghosh ,  Manish Sharma

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/311 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L21/28123 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/31116 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: Techniques are provided herein to form semiconductor devices that include one or more gate cuts having a very high aspect ratio (e.g., an aspect ratio of 5:1 or greater, such as 10:1). In an example, a semiconductor device includes a conductive material that is part of a transistor gate structure around or otherwise on a semiconductor region. The semiconductor region can be, for example, a fin of semiconductor material that extends between a source region and a drain region, or one or more nanowires or nanoribbons of semiconductor material that extend between a source region and a drain region. The gate structure may be interrupted between two transistors with a gate cut that extends through an entire thickness of the gate structure. A particular plasma etching process may be performed to form the gate cut with a very high height-to-width aspect ratio so as to enable densely integrated devices.

公开(公告)号：US20240088218A1

公开(公告)日：2024-03-14

申请号：US17943443

申请日：2022-09-13

Applicant: Intel Corporation

Inventor： Shao-Ming Koh ,  Leonard P. Guler ,  Gurpreet Singh ,  Manish Chandhok ,  Matthew J. Prince

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/778 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/778 ,  H01L29/78696

Abstract: Techniques are provided herein to form an integrated circuit having a grating pattern of gate cut structures such that a gate cut structure extends between the gate layers of adjacent semiconductor devices and between the source or drain regions (e.g., epitaxial regions) of the adjacent semiconductor devices. In an example, neighboring semiconductor devices each include a semiconductor region extending between a source region and a drain region, and a gate structure extending over the semiconductor regions of the neighboring semiconductor devices. In some such examples, a gate cut structure is present between each pair of neighboring semiconductor devices thus interrupting the gate structure and isolating the gate electrode of one semiconductor device from the gate electrode of the other semiconductor device. The gate cut structure further extends to separate the source or drain regions of the neighboring semiconductor devices. Subsequent processes allow neighboring gate or source or drain regions connections.

公开(公告)号：US11756833B2

公开(公告)日：2023-09-12

申请号：US17738968

申请日：2022-05-06

Applicant: Intel Corporation

Inventor： Sridhar Govindaraju ,  Matthew J. Prince

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L27/088 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/768 ,  H01L23/498 ,  H01L23/532 ,  H01L23/535 ,  H01L23/00 ,  H01L21/84 ,  H01L29/06 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/12 ,  H01L27/092

CPC classification number: H01L21/823437 ,  H01L21/31053 ,  H01L21/32115 ,  H01L21/7684 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/823475 ,  H01L23/49838 ,  H01L23/535 ,  H01L23/5329 ,  H01L24/16 ,  H01L27/0886 ,  H01L29/4238 ,  H01L29/42372 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/823871 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/0002

Abstract: Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed.

公开(公告)号：US11380592B2

公开(公告)日：2022-07-05

申请号：US17069265

申请日：2020-10-13

Applicant: INTEL CORPORATION

Inventor： Sridhar Govindaraju ,  Matthew J. Prince

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L27/088 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/768 ,  H01L23/498 ,  H01L23/532 ,  H01L23/535 ,  H01L23/00 ,  H01L21/84 ,  H01L29/06 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/12

Abstract: Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed.

公开(公告)号：US10468305B2

公开(公告)日：2019-11-05

申请号：US15415495

申请日：2017-01-25

Applicant: INTEL CORPORATION

Inventor： Sridhar Govindaraju ,  Matthew J. Prince

IPC: H01L23/00 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/423 ,  H01L27/088 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/768 ,  H01L23/498 ,  H01L23/532 ,  H01L23/535 ,  H01L21/84

Abstract: Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed.

公开(公告)号：US09761497B2

公开(公告)日：2017-09-12

申请号：US15008325

申请日：2016-01-27

Applicant: INTEL CORPORATION

Inventor： Sridhar Govindaraju ,  Matthew J. Prince

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L21/3105 ,  H01L21/321

CPC classification number: H01L21/823437 ,  H01L21/31053 ,  H01L21/32115 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/823475 ,  H01L23/49838 ,  H01L23/5329 ,  H01L23/535 ,  H01L24/16 ,  H01L27/0886 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66795 ,  H01L29/785 ,  H01L2224/16227

Abstract: Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed.

公开(公告)号：US20170133276A1

公开(公告)日：2017-05-11

申请号：US15415495

申请日：2017-01-25

Applicant: INTEL CORPORATION

Inventor： Sridhar Govindaraju ,  Matthew J. Prince

IPC: H01L21/8234 ,  H01L23/532 ,  H01L23/00 ,  H01L21/768 ,  H01L23/498 ,  H01L23/535 ,  H01L27/088

CPC classification number: H01L21/823437 ,  H01L21/31053 ,  H01L21/32115 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/823475 ,  H01L21/845 ,  H01L23/49838 ,  H01L23/5329 ,  H01L23/535 ,  H01L24/16 ,  H01L27/0886 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66795 ,  H01L29/785 ,  H01L2224/16225 ,  H01L2224/16227

Abstract: Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed.