公开(公告)号：US11830788B2

公开(公告)日：2023-11-28

申请号：US17303270

申请日：2021-05-25

Applicant: Intel Corporation

Inventor： Carl Naylor ,  Ashish Agrawal ,  Urusa Alaan ,  Christopher Jezewski ,  Mauro Kobrinsky ,  Kevin Lin ,  Abhishek Anil Sharma

IPC: H01L23/40 ,  H01L21/822 ,  H01L23/532 ,  H01L27/12 ,  H01L21/70

CPC classification number: H01L23/4012 ,  H01L21/707 ,  H01L21/8221 ,  H01L23/5329 ,  H01L27/1222

Abstract: An example relates to an integrated circuit including a semiconductor substrate, and a wiring layer stack located on the semiconductor substrate. The integrated circuit further includes a transistor embedded in the wiring layer stack. The transistor includes an embedded layer. The embedded layer has a thickness of less than 10 nm. The embedded layer includes at least one two-dimensional crystalline layer including more than 10% metal atoms. Further examples relate to methods for forming integrated circuits.

公开(公告)号：US11410928B2

公开(公告)日：2022-08-09

申请号：US16003031

申请日：2018-06-07

Applicant: Intel Corporation

Inventor： Mark Bohr ,  Mauro Kobrinsky ,  Marni Nabors

IPC: H01L21/768 ,  H01L23/528 ,  H01L21/762 ,  H01L21/8234 ,  H01L23/31 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L23/522 ,  H01L23/00

Abstract: Described herein are integrated circuit (IC) structures, devices, and methods associated with device layer interconnects. For example, an IC die may include a device layer including a transistor array along a semiconductor fin, and a device layer interconnect in the transistor array, wherein the device layer interconnect is in electrical contact with multiple different source/drain regions of the transistor array.

公开(公告)号：US11189585B2

公开(公告)日：2021-11-30

申请号：US16703298

申请日：2019-12-04

Applicant: Intel Corporation

Inventor： Brennen K. Mueller ,  Adel Elsherbini ,  Mauro Kobrinsky ,  Johanna Swan ,  Shawna Liff ,  Pooya Tadayon

IPC: H01L23/52 ,  H01L23/00

Abstract: An Integrated Circuit (IC) device comprising a first component, the first component comprising a first dielectric and a plurality of adjacent first interconnect structures within the first dielectric. The IC device comprising a second component, the second component comprising a second dielectric and a plurality of adjacent second interconnect structures within the second dielectric. A first of the second interconnect structures is in direct contact with a first of the first interconnect structures at a bond interface between the first and second components. A second of the first interconnect structures is set back a distance from a plane of the bond interface.

公开(公告)号：US10204855B2

公开(公告)日：2019-02-12

申请号：US14653033

申请日：2014-07-11

Applicant: Intel Corporation

Inventor： Alejandro Levander ,  Tatyana Andryushchenko ,  David Staines ,  Mauro Kobrinsky ,  Aleksandar Aleksov ,  Dilan Seneviratne ,  Javier Soto Gonzalez ,  Srinivas Pietambaram ,  Rafiqul Islam

IPC: H01L23/00 ,  H01L23/498 ,  B23B5/16 ,  B32B27/08 ,  B32B27/28 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/31 ,  H01L25/00 ,  H05K1/02

Abstract: Generally discussed herein are systems and methods that can include a stretchable and bendable device. According to an example a method can include (1) depositing a first elastomer material on a panel, (2) laminating trace material on the elastomer material, (3) processing the trace material to pattern the trace material into one or more traces and one or more bond pads, (4) attaching a die to the one or more bond pads, or (5) depositing a second elastomer material on and around the one or more traces, the bonds pads, and the die to encapsulate the one or more traces and the one or more bond pads in the first and second elastomer materials.

公开(公告)号：US20170179103A1

公开(公告)日：2017-06-22

申请号：US15450900

申请日：2017-03-06

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Mauro Kobrinsky ,  Johanna Swan ,  Rajendra C. Dias

IPC: H01L25/00 ,  H01L23/00

Abstract: Generally discussed herein are systems and apparatuses that can include apparatuses, systems, or method for a flexible, wire bonded device. According to an example an apparatus can include (1) a first rigid circuit comprising a first plurality of bond pads proximate to a first edge of the first rigid circuit, (2) a second rigid circuit comprising a second plurality of bond pads proximate to a first edge of the second rigid circuit, the second rigid circuit adjacent the first rigid circuit and the first edge of the second rigid circuit facing the first edge of the first rigid circuit, or (3) a first plurality of wire bonded wires, each wire bonded wire of the first plurality of wire bonded wires electrically and mechanically connected to a bond pad of the first plurality of bond pads and a bond pad of the second plurality of bond pads.

公开(公告)号：US12288746B2

公开(公告)日：2025-04-29

申请号：US16727747

申请日：2019-12-26

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Mauro Kobrinsky ,  Shawna Liff ,  Johanna Swan ,  Gerald Pasdast ,  Sathya Narasimman Tiagaraj

IPC: H01L23/52 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: An integrated circuit device may be formed including an electronic substrate and a metallization structure on the electronic substrate, wherein the metallization structure includes a first level comprising a first dielectric material layer, a second level on the first level, wherein the second level comprises a second dielectric material layer, a third level on the second level, wherein the third level comprises a third dielectric material layer, at least one power/ground structure in the second level, and at least one skip level via extending at least partially through the first dielectric material layer of the first level, through the second dielectric layer of the second level, and at least partially through the third dielectric material layer of the third level, wherein the at least one skip level via comprises a continuous conductive material.

公开(公告)号：US12199143B2

公开(公告)日：2025-01-14

申请号：US16727406

申请日：2019-12-26

Applicant: Intel Corporation

Inventor： Biswajeet Guha ,  Mauro Kobrinsky ,  Patrick Morrow ,  Oleg Golonzka ,  Tahir Ghani

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/027 ,  H01L21/306 ,  H01L21/84 ,  H01L27/12 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: Gate-all-around integrated circuit structures having a removed substrate, and methods of fabricating gate-all-around integrated circuit structures having a removed substrate, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack surrounds a channel region of the vertical arrangement of horizontal nanowires. A pair of non-discrete epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal nanowires. A pair of dielectric spacers is between the pair of non-discrete epitaxial source or drain structures and the gate stack. The pair of dielectric spacers and the gate stack have co-planar top surfaces. The pair of dielectric spacers, the gate stack and the pair of non-discrete epitaxial source or drain structures have co-planar bottom surfaces.

公开(公告)号：US20240243052A1

公开(公告)日：2024-07-18

申请号：US18622500

申请日：2024-03-29

Applicant: Intel Corporation

Inventor： Kevin L. Lin ,  Sukru Yemenicioglu ,  Patrick Morrow ,  Richard Schenker ,  Mauro Kobrinsky

IPC: H01L23/498 ,  H01L21/768 ,  H01L27/088 ,  H05K1/11 ,  H05K3/00 ,  H05K3/40

CPC classification number: H01L23/49827 ,  H01L21/76879 ,  H01L27/088 ,  H05K1/115 ,  H05K3/0094 ,  H05K3/4038

Abstract: An integrated circuit interconnect level including a lower metallization line vertically spaced from upper metallization lines. Lower metallization lines may be self-aligned to upper metallization lines enabling increased metallization line width without sacrificing line density for a given interconnect level. Combinations of upper and lower metallization lines within an interconnect metallization level may be designed to control intra-layer resistance/capacitance of integrated circuit interconnect. Dielectric material between two adjacent co-planar metallization lines may be recessed or deposited selectively to the metallization lines. Supplemental metallization may then be deposited and planarized. A top surface of the supplemental metallization may either be recessed to form lower metallization lines between upper metallization lines, or planarized with dielectric material to form upper metallization lines between lower metallization lines. Vias to upper and lower metallization line may extend another metallization level.

公开(公告)号：US20220415795A1

公开(公告)日：2022-12-29

申请号：US17358442

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Mohit Haran ,  Charles Wallace ,  Leanord Guler ,  Sukru Yemenicioglu ,  Mauro Kobrinsky ,  Tahir Ghani

IPC: H01L23/528 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/40 ,  H01L29/66

Abstract: Back-side transistor contacts that wrap around a portion of source and/or drain semiconductor bodies, related transistor structures, integrated circuits, systems, and methods of fabrication are disclosed. Such back-side transistor contacts are coupled to a top and a side of the source and/or drain semiconductor and extend to back-side interconnects. Coupling to top and side surfaces of the source and/or drain semiconductor reduces contact resistance and extending the metallization along the side reduces transistor cell size for improve device density.

公开(公告)号：US20220102268A1

公开(公告)日：2022-03-31

申请号：US17033375

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Urusa Alaan ,  Kevin L. Lin ,  Miriam Reshotko ,  Sarah Atanasov ,  Christopher Jezewski ,  Carl Naylor ,  Mauro Kobrinsky ,  Hui Jae Yoo

IPC: H01L23/522 ,  H01L21/768

Abstract: Integrated circuit interconnect structures including a metallization line with a bottom barrier material, and a metallization via lacking a bottom barrier material. Barrier material at a bottom of the metallization line may, along with barrier material on a sidewall of the metallization line, mitigate the diffusion or migration of fill metal from the line. An absence of barrier material at a bottom of the via may reduce via resistance and/or facilitate the use of a highly resistive barrier material that may enhance the scalability of interconnect structures. A number of masking materials and patterning techniques may be integrated into a dual damascene interconnect process to provide for both a barrier material and a low resistance via unburden by the barrier material.