公开(公告)号：US08996895B2

公开(公告)日：2015-03-31

申请号：US14317239

申请日：2014-06-27

Applicant: Intel Corporation

Inventor： Alon Naveh ,  Eliezer Weissmann ,  Ofer Nathan ,  Nadav Shulman

IPC: G06F1/00 ,  G06F1/32 ,  G06F13/24 ,  G06F15/00

CPC classification number: G06F1/3275 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3243 ,  G06F1/3246 ,  G06F1/3296 ,  Y02D10/152 ,  Y02D10/172

Abstract: A processor may include power management techniques to, dynamically, chose an optimal C-state for the processing core. The measurement of real workloads on the OSes exhibit two important observations (1) the bursts of high interrupt rate are interspersed between the low interrupt rate periods and long periods of high activity levels; and (2) the interrupt rate may, suddenly, fall below an interrupt rate (of 1 milli-second, for example) that is typical of the current operating systems (OS). Instead of determining the C-state based on the stale data stored in the counters, the power control logic may determine an optimal C-state by overriding the C-state determined by the OS or any other power monitoring logic. The power control logic may, dynamically, determine an optimal C-state based on the CPU idle residency times and variable rate wakeup events to match the expected wakeup event rate.

Abstract translation: 处理器可以包括动态地为处理核心选择最佳C状态的电源管理技术。 对操作系统的实际工作负载的测量表现出两个重要的观察结果：（1）高中断率的突发散布在低中断速率周期和长时间的高活动水平之间; 和（2）中断率可能突然降低到当前操作系统（OS）的典型值的中断速率（例如，1毫秒）。 功率控制逻辑可以基于存储在计数器中的陈旧数据来确定C状态，而不是通过覆盖由OS或任何其它功率监视逻辑确定的C状态来确定最佳C状态。 功率控制逻辑可以动态地基于CPU空闲驻留时间和可变速率唤醒事件来确定最佳C状态以匹配预期的唤醒事件速率。

公开(公告)号：US11703927B2

公开(公告)日：2023-07-18

申请号：US16833328

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Oren Zonensain ,  Roman Rechter ,  Almog Reshef ,  Maxim Levit ,  Nadav Shulman ,  Efraim Rotem

IPC: G06F1/00 ,  G06F11/30 ,  G06F1/28 ,  G01R31/52

CPC classification number: G06F1/28 ,  G01R31/52

Abstract: A performance management scheme for a processor based on leakage current measurement in field. The scheme performs the operations of detection and correction. The operation of detection measures per core leakage current in the field (e.g., using voltage regulator electrical current counters). The operation of correction changes the processor power management behavior. For example, processor cores showing high leakage degradation may be logically swapped with cores showing low leakage degradation.

公开(公告)号：US20220113779A1

公开(公告)日：2022-04-14

申请号：US17645202

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Ryan D. Wells ,  Itai Feit ,  Doron Rajwan ,  Nadav Shulman ,  Zeev Offen ,  Inder M. Sodhi

IPC: G06F1/28 ,  G06F1/324 ,  G06F1/3206 ,  G06F1/26

Abstract: In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.

公开(公告)号：US11243768B2

公开(公告)日：2022-02-08

申请号：US16259880

申请日：2019-01-28

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Eliezer Weissmann ,  Boris Ginzburg ,  Alon Naveh ,  Nadav Shulman ,  Ronny Ronen

IPC: G06F11/34 ,  G06F11/30 ,  G06F9/30 ,  G06F9/38 ,  G06F9/455 ,  G06F1/3234

Abstract: Disclosed embodiments relate to processing logic for performing function operations. In one example, and apparatus includes an execution unit within a processor to execute a code block, power management hardware coupled to the execution unit, wherein the power management hardware is to monitor a first execution of the code block, store a micro-architectural context of the processor in a metadata block associated with the code block, the micro-architectural context including performance data resulting from the first execution of the code block, the performance data comprising power and energy usage data, and power management related parameters, read the associated metadata block upon a second execution of the code block, and tune the second execution based on the performance data stored in the associated metadata block to increase efficiency of executing the code block.

公开(公告)号：US11188138B2

公开(公告)日：2021-11-30

申请号：US16206019

申请日：2018-11-30

Applicant: Intel Corporation

Inventor： Michael Bitan ,  Andrey Gabdulin ,  Efraim Rotem ,  Eli Efron ,  Nadav Shulman ,  David Ben Shimon ,  Nir Levitin ,  Esfir Natanzon

IPC: G06F1/3296 ,  G06F1/324 ,  G06F1/20

Abstract: In an embodiment, a processor includes a plurality of processing engines to execute instructions and a power management unit. The power management unit is to: control an operating frequency and a supply voltage according to a first voltage/frequency curve associated with a first temperature; and in response to a detection of a second temperature in the processor, increase the operating frequency to a second frequency based on a second voltage/frequency curve, wherein, at least one voltage of a first range of voltages, the second voltage/frequency curve specifies a higher frequency than the first voltage/frequency curve. Other embodiments are described and claimed.

公开(公告)号：US20210109562A1

公开(公告)日：2021-04-15

申请号：US17130982

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Daniel Ragland ,  Nadav Shulman ,  Louis Draghi

IPC: G06F1/10 ,  G06F1/08 ,  G06F1/3206 ,  G06F1/20 ,  G06F16/9035

Abstract: Methods, apparatus, and articles of manufacture to dynamically configure overclocking frequency have been disclosed. An example apparatus include a clock rate adjuster to cause a processor core to operate at a first overclocked clock rate; a comparator to compare a sensed temperature corresponding to the processor core to a threshold; and the clock rate adjuster to, when the sensed temperature satisfies the threshold, decrease a clock rate of the processor core from the first overclocked clock rate by a user-defined amount, the decreased clock rate being above a normal operating clock rate of the processor core.

公开(公告)号：US10474216B2

公开(公告)日：2019-11-12

申请号：US14971302

申请日：2015-12-16

Applicant: Intel Corporation

Inventor： Doron Rajwan ,  Dorit Shapira ,  Itai Feit ,  Nadav Shulman ,  Efraim (Efi) Rotem ,  Tal Kuzi ,  Eliezer Weissmann ,  Tomer Ziv ,  Nir Rosenzweig

IPC: G06F1/32 ,  G06F13/42 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3296

Abstract: A method and apparatus for providing power state information using in-band signaling are described. In one embodiment, an integrated circuit (IC) device comprises a controller operable to receive a command from a platform control bus, the command requesting data that is unrelated to information about a power state in which the IC resides; and control logic operable to obtain data for inclusion in a response to the command, wherein the controller is operable to send the response over a bus, the response containing at least a portion of the data responsive to the command and containing power state information for the IC.

公开(公告)号：US20190155606A1

公开(公告)日：2019-05-23

申请号：US16259880

申请日：2019-01-28

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Eliezer Weissmann ,  Boris Ginzburg ,  Alon Naveh ,  Nadav Shulman ,  Ronny Ronen

IPC: G06F9/30 ,  G06F9/455 ,  G06F9/38 ,  G06F11/34 ,  G06F1/3234

Abstract: Disclosed embodiments relate to processing logic for performing function operations. In one example, and apparatus includes an execution unit within a processor to execute a code block, power management hardware coupled to the execution unit, wherein the power management hardware is to monitor a first execution of the code block, store a micro-architectural context of the processor in a metadata block associated with the code block, the micro-architectural context including performance data resulting from the first execution of the code block, the performance data comprising power and energy usage data, and power management related parameters, read the associated metadata block upon a second execution of the code block, and tune the second execution based on the performance data stored in the associated metadata block to increase efficiency of executing the code block.

公开(公告)号：US10222851B2

公开(公告)日：2019-03-05

申请号：US15331051

申请日：2016-10-21

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Nir Rosenzweig ,  Doron Rajwan ,  Nadav Shulman ,  Gal Leibovich ,  Tomer Ziv ,  Amit Gabai ,  Jorge P. Rodriguez ,  Jeffrey A. Carlson

IPC: G06F1/32 ,  G06F1/324 ,  G05F1/10 ,  H03L7/08 ,  G06F1/28 ,  G06F1/3206

Abstract: A method and apparatus for providing proactive current protection. In one embodiment, the method comprises: prior to transitioning to a new state for an integrated circuit (IC), calculating a sum of expected powers for a plurality of domains in the IC by calculating an expected current for each of the plurality of domains based on an individual domain frequency in the new state and multiplying the expected current with its associated voltage for each of the plurality of domains for the new state; comparing the sum to a power limit; and if the sum is greater than the power limit, then reducing the individual domain frequency associated with at least one domain in the plurality of domains to maintain the total instantaneous power of the IC below the power limit.

公开(公告)号：US10114448B2

公开(公告)日：2018-10-30

申请号：US14322185

申请日：2014-07-02

Applicant: Intel Corporation

Inventor： Jawad Haj-Yihia ,  Eliezer Weissmann ,  Vijay S R Degalahal ,  Nadav Shulman ,  Tal Kuzi ,  Itay Franko ,  Amit Gur ,  Efraim Rotem

IPC: G06F1/00 ,  G06F1/32

Abstract: Methods and apparatus relating to autonomous C state mechanism and computational engine alignment for improved processor power efficiency. are described. An embodiment determines whether a semiconductor package should enter a package C state based on energy consumption values for entry into and exit from the package C state, an amount of time the semiconductor package stayed in the package C state previously, and one or more breakeven time points between the various package C states. Another embodiment detects a delay by an imaging computational unit of a processor to enter a low power consumption state relative to one or more other computational units of the processor. The logic causes the imaging computational unit to enter the low power consumption state in response to detection of the delay. Other embodiments are also disclosed and claimed.