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    FABRICATION OF UNDOPED HFO2 FERROELECTRIC LAYER USING PVD
    13.
    发明申请
    FABRICATION OF UNDOPED HFO2 FERROELECTRIC LAYER USING PVD 审中-公开

    公开(公告)号：US20200066511A1

    公开(公告)日：2020-02-27

    申请号：US16113159

    申请日：2018-08-27

    Applicant: Intel Corporation

    Inventor： Ilya KARPOV ,  Brian DOYLE ,  Prashant MAJHI ,  Abhishek SHARMA ,  Ravi PILLARISETTY

    IPC: H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  H01G4/12 ,  C23C14/08 ,  C23C14/34 ,  C23C14/54

    Abstract: Embodiments disclosed herein comprise a ferroelectric material layer and methods of forming such materials. In an embodiment, the ferroelectric material layer comprises hafnium oxide with an orthorhombic phase. In an embodiment, the ferroelectric material layer may also comprise trace elements of a working gas. Additional embodiments may comprise: a semiconductor channel, a source region on a first end of the semiconductor channel, a drain region on a second end of the semiconductor channel, a gate electrode over the semiconductor channel, and a gate dielectric between the gate electrode and the semiconductor channel. In an embodiment, the gate dielectric includes a ferroelectric hafnium oxide. In an embodiment, the hafnium oxide is substantially free from dopants.

    1S-1T FERROELECTRIC MEMORY
    14.
    发明申请
    1S-1T FERROELECTRIC MEMORY 有权

    公开(公告)号：US20220130443A1

    公开(公告)日：2022-04-28

    申请号：US17570249

    申请日：2022-01-06

    Applicant: Intel Corporation

    Inventor： Abhishek A. SHARMA ,  Brian S. DOYLE ,  Ravi PILLARISETTY ,  Prashant MAJHI ,  Elijah V. KARPOV

    IPC: G11C11/22 ,  H01L27/11585

    Abstract: A 1S-1T ferroelectric memory cell is provided that include a transistor and a two-terminal selector device. The transistor exhibits a low conductive state and a high conductive state (channel resistance), depending on drive voltage. The two-terminal selector device exhibits one of an ON-state and an OFF-state depending upon whether the transistor is in its low conductive state or its high conductive state. The transistor may be, for instance, a ferroelectric gate vertical transistor. Modulation of a polarization state of ferroelectric material of the vertical transistor may be utilized to switch the state of the selector device. The memory cell may thus selectively be operated in one of an ON-state and an OFF-state depending upon whether the selector device is in its ON-state or OFF-state.

    BI-AXIAL TENSILE STRAINED GE CHANNEL FOR CMOS
    19.
    发明申请
    BI-AXIAL TENSILE STRAINED GE CHANNEL FOR CMOS 有权
    用于CMOS的双向拉伸应变通道

    公开(公告)号：US20160293601A1

    公开(公告)日：2016-10-06

    申请号：US15037618

    申请日：2013-12-27

    Applicant: INTEL CORPORATION

    Inventor： Prashant MAJHI ,  Niloy MUKHERJEE ,  Ravi PILLARISETTY ,  Willy RACHMADY ,  Robert S. CHAU

    IPC: H01L27/092 ,  H01L29/165 ,  H01L29/06 ,  H01L29/10 ,  H01L21/8238

    CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/78669 ,  H01L29/78684

    Abstract: An apparatus comprising a complimentary metal oxide semiconductor (CMOS) inverter including an n-channel metal oxide semiconductor field effect transistor (MOSFET); and a p-channel MOSFET, wherein a material of a channel in the n-channel MOSFET and a material of a channel in the p-channel MOSFET is subject to a bi-axial tensile strain. A method including forming an n-channel metal oxide semiconductor field effect transistor (MOSFET); forming a p-channel MOSFET; and connecting the gate electrodes and the drain regions of the n-channel MOSFET and the p-channel MOSFET, wherein a material of the channel in the n-channel MOSFET and a material of the channel in the p-channel MOSFET is subject to a bi-axial tensile strain.

    Abstract translation: 一种包括具有n沟道金属氧化物半导体场效应晶体管（MOSFET）的互补金属氧化物半导体（CMOS）反相器的装置; 以及p沟道MOSFET，其中n沟道MOSFET中的沟道材料和p沟道MOSFET中的沟道的材料经受双轴向拉伸应变。 一种包括形成n沟道金属氧化物半导体场效应晶体管（MOSFET）的方法; 形成p沟道MOSFET; 以及连接n沟道MOSFET和p沟道MOSFET的栅电极和漏极区，其中n沟道MOSFET中的沟道的材料和p沟道MOSFET中的沟道的材料受到 双向拉伸应变。

    DOUBLE SELECTOR ELEMENT FOR LOW VOLTAGE BIPOLAR MEMORY DEVICES
    20.
    发明申请
    DOUBLE SELECTOR ELEMENT FOR LOW VOLTAGE BIPOLAR MEMORY DEVICES 审中-公开

    公开(公告)号：US20200235162A1

    公开(公告)日：2020-07-23

    申请号：US16632065

    申请日：2017-09-27

    Applicant: Intel Corporation

    Inventor： Prashant MAJHI ,  Ravi PILLARISETTY ,  Elijah V. KARPOV ,  Brian S. DOYLE ,  Abhishek A. SHARMA

    IPC: H01L27/24 ,  H01L27/22 ,  H01L45/00

    Abstract: Embedded non-volatile memory structures having double selector elements are described. In an example, a memory device includes a word line. A double selector element is above the word line. The double selector element includes a first selector material layer, a second selector material layer different than the first selector material layer, and a conductive layer directly between the first selector material layer and the second selector material layer. A bipolar memory element is above the word line. A conductive electrode is between the double selector element and the bipolar memory element. A bit line is above the word line.

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