公开(公告)号：US20230369206A1

公开(公告)日：2023-11-16

申请号：US17743913

申请日：2022-05-13

Applicant: Intel Corporation

Inventor： Robert L. BRISTOL ,  Kevin Lai LIN ,  Clifford J. ENGEL

IPC: H01L23/528 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/76816 ,  H01L21/76877

Abstract: Lithographic methodologies involving, and apparatuses suitable for, inline circuit edits are described. In an example, an integrated circuit structure includes a plurality of conductive lines in a dielectric layer, individual ones of the plurality of conductive lines along a direction and spaced at a same interval. A conductive structure is in the dielectric layer, the conductive structure laterally between but not in contact with a pair of the plurality of conductive lines.

公开(公告)号：US20210397084A1

公开(公告)日：2021-12-23

申请号：US17464393

申请日：2021-09-01

Applicant: Intel Corporation

Inventor： James M. BLACKWELL ,  Robert L. BRISTOL ,  Marie KRYSAK ,  Florian GSTREIN ,  Eungnak HAN ,  Kevin L. LIN ,  Rami HOURANI ,  Shane M. HARLSON

IPC: G03F7/00 ,  H01L21/027 ,  H01L21/768 ,  G03F7/40

Abstract: Lined photoresist structures to facilitate fabricating back end of line (BEOL) interconnects are described. In an embodiment, a hard mask has recesses formed therein, wherein liner structures are variously disposed each on a sidewall of a respective recess. Photobuckets comprising photoresist material are also variously disposed in the recesses. The liner structures variously serve as marginal buffers to mitigate possible effects of misalignment in the exposure of photoresist material to photons or an electron beam. In another embodiment, a recess has disposed therein a liner structure and a photobucket that are both formed by self-assembly of a photoresist-based block-copolymer.

公开(公告)号：US20210050261A1

公开(公告)日：2021-02-18

申请号：US17085882

申请日：2020-10-30

Applicant: Intel Corporation

Inventor： Kevin LIN ,  Robert L. BRISTOL ,  Richard E. SCHENKER

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: Subtractive plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects is described. In an example, a back end of line (BEOL) metallization layer for a semiconductor structure includes an inter-layer dielectric (ILD) layer disposed above a substrate. A plurality of conductive lines is disposed in the ILD layer along a first direction. A conductive tab is disposed in the ILD layer, the conductive tab coupling two of the plurality of conductive lines along a second direction orthogonal to the first direction. A conductive via is coupled to one of the plurality of conductive lines, the conductive via having a via hardmask thereon. An uppermost surface of each of the ILD layer, the plurality of conductive lines, the conductive tab, and the via hardmask is planar with one another.

公开(公告)号：US20190043731A1

公开(公告)日：2019-02-07

申请号：US16075555

申请日：2016-04-08

Applicant: Intel Corporation

Inventor： Robert L. BRISTOL ,  Marie KRYSAK ,  James M. BLACKWELL ,  Florian GSTREIN ,  Kent N. FRASURE

IPC: H01L21/311 ,  G03F7/004 ,  G03F7/039 ,  G03F7/20 ,  G03F7/38 ,  H01L21/027 ,  H01L21/033

Abstract: Two-stage bake photoresists with releasable quenchers for fabricating back end of line (BEOL) interconnects are described. In an example, a photolyzable composition includes an acid-deprotectable photoresist material having substantial transparency at a wavelength, a photo-acid-generating (PAG) component having substantial transparency at the wavelength, and a base-generating component having substantial absorptivity at the wavelength.

公开(公告)号：US20240071917A1

公开(公告)日：2024-02-29

申请号：US18384582

申请日：2023-10-27

Applicant: Intel Corporation

Inventor： Richard E. SCHENKER ,  Robert L. BRISTOL ,  Kevin L. LIN ,  Florian GSTREIN ,  James M. BLACKWELL ,  Marie KRYSAK ,  Manish CHANDHOK ,  Paul A. NYHUS ,  Charles H. WALLACE ,  Curtis W. WARD ,  Swaminathan SIVAKUMAR ,  Elliot N. TAN

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L23/528 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L27/0886 ,  H01L29/7848

Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

公开(公告)号：US20200066629A1

公开(公告)日：2020-02-27

申请号：US16346873

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Richard E. SCHENKER ,  Robert L. BRISTOL ,  Kevin L. LIN ,  Florian GSTREIN ,  James M. BLACKWELL ,  Marie KRYSAK ,  Manish CHANDHOK ,  Paul A. NYHUS ,  Charles H. WALLACE ,  Curtis W. WARD ,  Swaminathan SIVAKUMAR ,  Elliot N. TAN

IPC: H01L23/528 ,  H01L27/088 ,  H01L23/532 ,  H01L29/78 ,  H01L23/522

Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

公开(公告)号：US20200066521A1

公开(公告)日：2020-02-27

申请号：US16489331

申请日：2017-03-31

Applicant: INTEL CORPORATION

Inventor： Kevin LIN ,  Rami HOURANI ,  Elliot N. TAN ,  Manish CHANDHOK ,  Anant H. JAHAGIRDAR ,  Robert L. BRISTOL ,  Richard E. SCHENKER ,  Aaron Douglas LILAK

IPC: H01L21/033 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/32 ,  H01L21/3115

Abstract: A computing device including tight pitch features and a method of fabricating a computing device using colored spacer formation is disclosed. The computing device includes a memory and an integrated circuit coupled to the memory. The integrated circuit includes a first multitude of features above a substrate. The integrated circuit die includes a second multitude of features above the substrate. The first multitude of features and the second multitude of features are same features disposed in a first direction. The first multitude of features interleave with the second multitude of features. The first multitude of features has a first size and the second multitude of features has a second size.

公开(公告)号：US20190259935A1

公开(公告)日：2019-08-22

申请号：US16346872

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Jasmeet S. CHAWLA ,  Sasikanth MANIPATRUNI ,  Robert L. BRISTOL ,  Chia-Ching LIN ,  Dmitri E. NIKONOV ,  Ian A. YOUNG

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: Magneto-electric spin orbital (MESO) structures having functional oxide vias, and method of fabricating magneto-electric spin orbital (MESO) structures having functional oxide vias, are described. In an example, a magneto-electric spin orbital (MESO) device includes a source region and a drain region in or above a substrate. A first via contact is on the source region. A second via contact is on the drain region, the second via contact laterally adjacent to the first via contact. A plurality of alternating ferromagnetic material lines and non-ferromagnetic conductive lines is above the first and second via contacts. A first of the ferromagnetic material lines is on the first via contact, and a second of the ferromagnetic material lines is on the second via contact. A spin orbit coupling (SOC) via is on the first of the ferromagnetic material lines. A functional oxide via is on the second of the ferromagnetic material lines.

公开(公告)号：US20190244806A1

公开(公告)日：2019-08-08

申请号：US16343385

申请日：2016-12-02

Applicant: Intel Corporation

Inventor： Robert L. BRISTOL ,  Kevin L. LIN ,  James M. BLACKWELL

IPC: H01L21/027 ,  H01L21/033 ,  H01L21/768

Abstract: Surface-aligned lithographic patterning approaches for back end of line (BEOL) interconnect fabrication, and the resulting structures, are described. In an example, an integrated circuit structure includes a substrate. A plurality of alternating first and second conductive lines is along a first direction of a back end of line (BEOL) metallization layer in a first inter-layer dielectric (ILD) layer above the substrate. A conductive via is on and electrically coupled to one of the conductive lines of the plurality of alternating first and second conductive lines, the conductive via centered over the one of the conductive lines. A second ILD layer is above plurality of alternating first and second conductive lines and laterally adjacent to the conductive via. The second ILD layer has an uppermost surface substantially co-planar with the flat top surface of the conductive via.

公开(公告)号：US20190165270A1

公开(公告)日：2019-05-30

申请号：US16320789

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Kevin L. LIN ,  Sarah E. ATANASOV ,  Kevin P. O'BRIEN ,  Robert L. BRISTOL

IPC: H01L45/00 ,  H01L27/24

Abstract: Spacer-based patterning for tight-pitch and low-variability random access memory (RAM) bit cells, and the resulting structures, are described. In an example, a semiconductor structure includes a substrate having a top layer. An array of non-volatile random access memory (RAM) bit cells is disposed on the top layer of the substrate. The array of non-volatile RAM bit cells includes columns of non-volatile RAM bit cells along a first direction and rows of non-volatile RAM bit cells along a second direction orthogonal to the first direction. A plurality of recesses is in the top layer of the substrate, along the first direction between columns of the array of non-volatile RAM bit cells.