公开(公告)号：US10903114B2

公开(公告)日：2021-01-26

申请号：US16582923

申请日：2019-09-25

Applicant: Intel Corporation

Inventor： Yuriy V. Shusterman ,  Flavio Griggio ,  Tejaswi K. Indukuri ,  Ruth A. Brain

IPC: H01L23/48 ,  H01L23/52 ,  H01L21/768 ,  H01L23/532 ,  H01L21/321 ,  H01L21/3213 ,  H01L23/31 ,  H01L23/528

Abstract: Techniques are disclosed for providing a decoupled via fill. Given a via trench, a first barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first metal fill is blanket deposited into the trench. The non-selective deposition is subsequently recessed so that only a portion of the trench is filled with the first metal. The previously deposited first barrier layer is removed along with the first metal, thereby re-exposing the upper sidewalls of the trench. A second barrier layer is conformally deposited onto the top of the first metal and the now re-exposed trench sidewalls. A second metal fill is blanket deposited into the remaining trench. Planarization and/or etching can be carried out as needed for subsequent processing. Thus, a methodology for filling high aspect ratio vias using a dual metal process is provided. Note, however, the first and second fill metals may be the same.

公开(公告)号：US10811595B2

公开(公告)日：2020-10-20

申请号：US16073687

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： Kevin J. Lee ,  Oleg Golonzka ,  Tahir Ghani ,  Ruth A. Brain ,  Yih Wang

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  H01L43/10 ,  H01L43/14

Abstract: Techniques are disclosed for forming a logic device including integrated spin-transfer torque magnetoresistive random-access memory (STT-MRAM). In accordance with some embodiments, one or more magnetic tunnel junction (MTJ) devices may be formed within a given back-end-of-line (BEOL) interconnect layer of a host logic device. A given MTJ device may be formed, in accordance with some embodiments, over an electrically conductive layer configured to serve as a pedestal layer for the MTJ's constituent magnetic and insulator layers. In accordance with some embodiments, one or more conformal spacer layers may be formed over sidewalls of a given MTJ device and attendant pedestal layer, providing protection from oxidation and corrosion. A given MTJ device may be electrically coupled with an underlying interconnect or other electrically conductive feature, for example, by another intervening electrically conductive layer configured to serve as a thin via, in accordance with some embodiments.

公开(公告)号：US20200185271A1

公开(公告)日：2020-06-11

申请号：US16637930

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Charles H. WALLACE ,  Reken PATEL ,  Hyunsoo PARK ,  Mohit K. HARAN ,  Debashish BASU ,  Curtis W. WARD ,  Ruth A. Brain

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/522

Abstract: Conductive via and metal line end fabrication is described. In an example, an interconnect structure includes a first inter-layer dielectric (ILD) on a hardmask layer, where the ILD includes a first ILD opening and a second ILD opening. The interconnect structure further includes an etch stop layer (ESL) on the ILD layer, where the ESL includes a first ESL opening aligned with the first ILD opening to form a first via opening, and where the ESL layer includes a second ESL opening aligned with the second ILD opening. The interconnect structure further includes a first via in the first via opening, a second ILD layer on the first ESL, and a metal line in the second ILD layer, where the metal line is in contact with the first via, and where the metal line includes a first metal opening, and where the metal line includes a second metal opening aligned with the second ILD opening and the ESL opening to form a second via opening. The interconnect structure further includes a metal line end in the first metal opening and further includes a second via in the metal line, where the second via is in the second via opening.

公开(公告)号：US20190122982A1

公开(公告)日：2019-04-25

申请号：US16302692

申请日：2016-06-22

Applicant: Intel Corporation

Inventor： Rami Hourani ,  Marie Krysak ,  Florian Gstrein ,  Ruth A. Brain ,  Mark T. Bohr ,  Manish Chandhok

IPC: H01L23/522 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/02

CPC classification number: H01L23/5226 ,  H01L21/02172 ,  H01L21/76224 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/823475 ,  H01L23/528 ,  H01L2221/1063

Abstract: An embodiment includes an apparatus comprising: a metal layer comprising a plurality of interconnect lines on a plurality of vias; an additional metal layer comprising first, second, and third interconnect lines on first, second, and third vias; the first and third vias coupling the first and third interconnect lines to two of the plurality of interconnect lines; a lateral interconnect, included entirely within the additional metal layer, directly connected to each of the first, second, and third interconnect lines; and an insulator layer included entirely between two sidewalls of the second via. Other embodiments are described herein.

公开(公告)号：US09899255B2

公开(公告)日：2018-02-20

申请号：US15528427

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： Rami Hourani ,  Marie Krysak ,  Florian Gstrein ,  Ruth A. Brain ,  Mark T. Bohr

IPC: H01L29/06 ,  H01L21/768 ,  H01L23/528 ,  H01L23/31

CPC classification number: H01L21/76807 ,  H01L21/76831 ,  H01L23/3171 ,  H01L23/5226 ,  H01L23/528 ,  H01L2221/1031 ,  H01L2221/1063

Abstract: Techniques are disclosed for insulating or electrically isolating select vias within a given interconnect layer, so a conductive routing can skip over those select isolated vias to reach other vias or interconnects in that same layer. Such a via blocking layer may be selectively implemented in any number of locations within a given interconnect as needed. Techniques for forming the via blocking layer are also provided, including a first methodology that uses a sacrificial passivation layer to facilitate selective deposition of insulator material that form the via blocking layer, a second methodology that uses spin-coating of wet-recessible polymeric formulations to facilitate selective deposition of insulator material that form the via blocking layer, and a third methodology that uses spin-coating of nanoparticle formulations to facilitate selective deposition of insulator material that form the via blocking layer. Harmful etching processes typically associated with conformal deposition processes is avoided.

公开(公告)号：US20160233217A1

公开(公告)日：2016-08-11

申请号：US15132037

申请日：2016-04-18

Applicant: Intel Corporation

Inventor： Ruth A. Brain

IPC: H01L27/108 ,  H01L21/768 ,  H01L23/532 ,  H01L49/02 ,  H01L23/528

CPC classification number: H01L28/60 ,  G06F1/184 ,  H01L21/02148 ,  H01L21/0217 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/31144 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76877 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/5329 ,  H01L27/10805 ,  H01L27/10814 ,  H01L27/1085 ,  H01L27/10852 ,  H01L27/10885 ,  H01L28/40 ,  H01L28/90 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Capacitor structures for integrated circuit devices are provided. Capacitors include proximate dense or highly dense etchstop layers. The dense or highly dense etchstop layer is, for example, a high-k material. Capacitors are, for example, metal-insulator-metal (MIM) capacitors and are useful in DRAM (dynamic random access memory) and eDRAM (embedded dynamic random access memory) structures.

公开(公告)号：US11417567B2

公开(公告)日：2022-08-16

申请号：US16347184

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Florian Gstrein ,  Eungnak Han ,  Rami Hourani ,  Ruth A. Brain ,  Paul A. Nyhus ,  Manish Chandhok ,  Charles H. Wallace ,  Chi-Hwa Tsang

IPC: H01L21/768 ,  H01L21/027 ,  H01L23/522 ,  H01L23/528

Abstract: Conductive cap-based approaches for conductive via fabrication is described. In an example, an integrated circuit structure includes a plurality of conductive lines in an ILD layer above a substrate. Each of the conductive lines is recessed relative to an uppermost surface of the ILD layer. A plurality of conductive caps is on corresponding ones of the plurality of conductive lines, in recess regions above each of the plurality of conductive lines. A hardmask layer is on the plurality of conductive caps and on the uppermost surface of the ILD layer. The hardmask layer includes a first hardmask component on and aligned with the plurality of conductive caps, and a second hardmask component on an aligned with regions of the uppermost surface of the ILD layer. A conductive via is in an opening in the hardmask layer and on a conductive cap of one of the plurality of conductive lines.

公开(公告)号：US11068640B2

公开(公告)日：2021-07-20

申请号：US16649588

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Ranjith Kumar ,  Mark T. Bohr ,  Ruth A. Brain ,  Marni Nabors ,  Tai-Hsuan Wu ,  Sourav Chakravarty

IPC: G06F30/3953 ,  G06F113/18 ,  G06F115/08 ,  H01L23/50 ,  H01L23/522

Abstract: An integrated circuit structure includes a metal level comprising a plurality of interconnect lines along a first direction. A cell is on the metal level, wherein one or more of the plurality of interconnect lines that extend through the cell comprise a power shared track that is segmented inside the cell into one or more power segments and one or more signal segments so that both power and signals share a same track.

公开(公告)号：US10672650B2

公开(公告)日：2020-06-02

申请号：US15898618

申请日：2018-02-18

Applicant: INTEL CORPORATION

Inventor： Rami Hourani ,  Marie Krysak ,  Florian Gstrein ,  Ruth A. Brain ,  Mark T. Bohr

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L23/31

Abstract: Techniques are disclosed for insulating or electrically isolating select vias within a given interconnect layer, so a conductive routing can skip over those select isolated vias to reach other vias or interconnects in that same layer. Such a via blocking layer may be selectively implemented in any number of locations within a given interconnect as needed. Techniques for forming the via blocking layer are also provided, including a first methodology that uses a sacrificial passivation layer to facilitate selective deposition of insulator material that form the via blocking layer, a second methodology that uses spin-coating of wet-recessible polymeric formulations to facilitate selective deposition of insulator material that form the via blocking layer, and a third methodology that uses spin-coating of nanoparticle formulations to facilitate selective deposition of insulator material that form the via blocking layer. Harmful etching processes typically associated with conformal deposition processes is avoided.

公开(公告)号：US10593626B2

公开(公告)日：2020-03-17

申请号：US15723083

申请日：2017-10-02

Applicant: Intel Corporation

Inventor： Ruth A. Brain ,  Kevin J. Fischer ,  Michael A. Childs

IPC: H01L23/532 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L21/311

Abstract: A method including forming a dielectric layer on a contact point of an integrated circuit structure; forming a hardmask including a dielectric material on a surface of the dielectric layer; and forming at least one via in the dielectric layer to the contact point using the hardmask as a pattern. An apparatus including a circuit substrate including at least one active layer including a contact point; a dielectric layer on the at least one active layer; a hardmask including a dielectric material having a least one opening therein for an interconnect material; and an interconnect material in the at least one opening of the hardmask and through the dielectric layer to the contact point.