公开(公告)号：US09753529B2

公开(公告)日：2017-09-05

申请号：US15158271

申请日：2016-05-18

Applicant: Intel Corporation

Inventor： Mahesh Wagh ,  Su Wei Lim

IPC: G08C17/00 ,  G06F1/32 ,  H04W52/02 ,  G06F9/44 ,  G06F13/42

CPC classification number: G06F1/3287 ,  G06F1/3253 ,  G06F1/3278 ,  G06F9/4418 ,  G06F13/4295 ,  H04W52/0203 ,  Y02D10/151 ,  Y02D10/157 ,  Y02D70/1222 ,  Y02D70/1226 ,  Y02D70/1242 ,  Y02D70/1262 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/164 ,  Y02D70/166

Abstract: Systems, apparatuses, and method for synchronizing port entry into a lowest power state are described. All logic of a port placed into an intermediate state prior to entry into the lowest power state.

公开(公告)号：US09588922B2

公开(公告)日：2017-03-07

申请号：US14668013

申请日：2015-03-25

Applicant: Intel Corporation

Inventor： Mikal C. Hunsaker ,  Su Wei Lim ,  Ricardo E. James

IPC: G06F13/00 ,  G06F13/364 ,  G06F1/06 ,  G06F1/24 ,  G06F13/42 ,  G06F11/07 ,  G06F11/10 ,  G06F11/22 ,  G06F13/12 ,  G06F13/40 ,  G06F11/30 ,  G06F13/16

CPC classification number: G06F13/364 ,  G06F1/06 ,  G06F1/24 ,  G06F11/0727 ,  G06F11/0745 ,  G06F11/1004 ,  G06F11/1072 ,  G06F11/221 ,  G06F11/2289 ,  G06F11/3027 ,  G06F13/00 ,  G06F13/122 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/423 ,  G06F13/4234 ,  G06F13/4282 ,  G06F13/4291 ,  G11C29/52

Abstract: Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.

Abstract translation: 具有组件间通信能力的分量设备和具有这种组件设备的系统在此被公开。 在实施例中，这样的组件可以包括多个控制引脚，包括时钟引脚，多个数据引脚和逻辑单元。 逻辑单元可以被配置为通过时钟引脚从另一个组件接收时钟信号，以通过所选择的一个控制和数据引脚向另一个组件提供警报信号，以启动与其他组件的交易，以便接收 通过数据引脚响应来自其他组件的警报信号，以确定事务的性质的状态请求，并且通过数据引脚向另一个组件响应状态请求来提供表示事务性质的状态。 提供警报信号，接收状态请求和提供状态可以参考时钟信号。 可以公开或要求保护其他实施例。

公开(公告)号：US20160085707A1

公开(公告)日：2016-03-24

申请号：US14801880

申请日：2015-07-17

Applicant: Intel Corporation

Inventor： Ting Lok Song ,  Su Wei Lim ,  Mikal C. Hunsaker ,  Hooi Kar Loo

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4022 ,  G06F13/385 ,  G06F13/387 ,  G06F13/4027 ,  G06F13/4282

Abstract: In some embodiments, an electronic system includes a processor, a memory in communication with the processor, a bus in communication with the processor, an Express Card controller coupled to the bus, the Express Card controller providing an interface to an external device, a USB3 controller coupled to the bus and in communication with the Express Card controller, and a PCIE controller coupled to the bus and in communication with the Express Card controller. The Express Card controller may be configured to determine whether the external device is a USB3 device or a PCIE device and to switch between the USB3 controller and the PCIE controller based on the state of a USB3 select pin strap. Other embodiments are disclosed and claimed.

Abstract translation: 在一些实施例中，电子系统包括处理器，与处理器通信的存储器，与处理器通信的总线，耦合到总线的Express卡控制器，提供与外部设备的接口的Express卡控制器，USB3 控制器耦合到总线并与Express卡控制器通信，以及耦合到总线并与Express卡控制器通信的PCIE控制器。 Express卡控制器可以被配置为基于USB3选择引脚带的状态来确定外部设备是USB3设备还是PCIE设备，并且在USB3控制器和PCIE控制器之间切换。 公开和要求保护其他实施例。

公开(公告)号：US09274987B2

公开(公告)日：2016-03-01

申请号：US14668028

申请日：2015-03-25

Applicant: Intel Corporation

Inventor： Mikal C. Hunsaker ,  Su Wei Lim ,  Ricardo E. James

IPC: G06F13/00 ,  G06F13/364 ,  G06F1/06 ,  G06F1/24 ,  G06F13/42 ,  G06F11/07 ,  G06F11/10 ,  G06F11/22 ,  G06F13/12 ,  G06F13/40 ,  G06F11/30 ,  G06F13/16

CPC classification number: G06F13/364 ,  G06F1/06 ,  G06F1/24 ,  G06F11/0727 ,  G06F11/0745 ,  G06F11/1004 ,  G06F11/1072 ,  G06F11/221 ,  G06F11/2289 ,  G06F11/3027 ,  G06F13/00 ,  G06F13/122 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/423 ,  G06F13/4234 ,  G06F13/4282 ,  G06F13/4291 ,  G11C29/52

Abstract: Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.

Abstract translation: 具有组件间通信能力的分量设备和具有这种组件设备的系统在此被公开。 在实施例中，这样的组件可以包括多个控制引脚，包括时钟引脚，多个数据引脚和逻辑单元。 逻辑单元可以被配置为通过时钟引脚从另一个组件接收时钟信号，以通过所选择的一个控制和数据引脚向另一个组件提供警报信号，以启动与其他组件的交易，以便接收 通过数据引脚响应来自其他组件的警报信号，以确定事务的性质的状态请求，并且通过数据引脚向另一个组件响应状态请求来提供表示事务性质的状态。 提供警报信号，接收状态请求和提供状态可以参考时钟信号。 可以公开或要求保护其他实施例。

公开(公告)号：US12001353B2

公开(公告)日：2024-06-04

申请号：US17819390

申请日：2022-08-12

Applicant: Intel Corporation

Inventor： Joon Teik Hor ,  Ting Lok Song ,  Mahesh Wagh ,  Su Wei Lim

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/1652 ,  G06F13/4022 ,  G06F13/4269

Abstract: In one embodiment, an apparatus includes an arbitration circuit with virtual link state machines to virtualize link states associated with multiple communication protocol stacks. The apparatus further includes a physical circuit coupled to the arbitration circuit and to interface with a physical link, where the physical circuit, in response to a retraining of the physical link, is to cause a plurality of the virtual link state machines to synchronize with corresponding virtual link state machines associated with a second side of the physical link, and where at least one of the communication protocol stacks is to remain in a low power state during the retraining and the synchronization. Other embodiments are described and claimed.

公开(公告)号：US11442876B2

公开(公告)日：2022-09-13

申请号：US16426361

申请日：2019-05-30

Applicant: Intel Corporation

Inventor： Joon Teik Hor ,  Ting Lok Song ,  Mahesh Wagh ,  Su Wei Lim

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

Abstract: In one embodiment, an apparatus includes an arbitration circuit with virtual link state machines to virtualize link states associated with multiple communication protocol stacks. The apparatus further includes a physical circuit coupled to the arbitration circuit and to interface with a physical link, where the physical circuit, in response to a retraining of the physical link, is to cause a plurality of the virtual link state machines to synchronize with corresponding virtual link state machines associated with a second side of the physical link, and where at least one of the communication protocol stacks is to remain in a low power state during the retraining and the synchronization. Other embodiments are described and claimed.

公开(公告)号：US10776302B2

公开(公告)日：2020-09-15

申请号：US16373472

申请日：2019-04-02

Applicant: Intel Corporation

Inventor： Joon Teik Hor ,  Ting Lok Song ,  Mahesh Wagh ,  Su Wei Lim

IPC: G06F13/40 ,  G06F13/38 ,  G06F13/42 ,  G06F13/16

Abstract: Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.

公开(公告)号：US20190102335A1

公开(公告)日：2019-04-04

申请号：US15721560

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Siang Lin Tan ,  Su Wei Lim ,  Ming Chew Lee ,  Ofer Nathan

IPC: G06F13/40 ,  G06F13/42 ,  G06F13/20

Abstract: An apparatus is provided which comprises: an input/output (I/O) port; an adaptor; a physical layer to interface between the I/O port and the adaptor; a first controller associated with a first type of communication; and a second controller associated with a second type of communication, wherein the adaptor is to selectively couple the I/O port, via the physical layer, to one of the first controller or the second controller, based at least in part on a type of device coupled to the I/O port.

公开(公告)号：US20190095554A1

公开(公告)日：2019-03-28

申请号：US15718110

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Eng Hun Ooi ,  Su Wei Lim ,  Kuan Hua Tan ,  Prashanth Kalluraya

IPC: G06F17/50 ,  G06F13/42

Abstract: Aspects of the embodiments are directed to systems and methods for emulating a PCIe root complex integrated endpoint. The systems and methods can include hardware logic implemented in a root complex system-on-chip and/or a connected device. The hardware can receive a request message to access one or more registers of a hardware device; determine that the request message includes a request to access one or more Peripheral Component Interconnect Express (PCIe)-specific registers; and respond to the request message without providing information associated with the one or more PCIe-specific registers.

公开(公告)号：US10229080B2

公开(公告)日：2019-03-12

申请号：US14801880

申请日：2015-07-17

Applicant: Intel Corporation

Inventor： Ting Lok Song ,  Su Wei Lim ,  Mikal C. Hunsaker ,  Hooi Kar Loo

IPC: G06F13/20 ,  G06F13/40 ,  G06F13/38 ,  G06F13/42

Abstract: In some embodiments, an electronic system includes a processor, a memory in communication with the processor, a bus in communication with the processor, an Express Card controller coupled to the bus, the Express Card controller providing an interface to an external device, a USB3 controller coupled to the bus and in communication with the Express Card controller, and a PCIE controller coupled to the bus and in communication with the Express Card controller. The Express Card controller may be configured to determine whether the external device is a USB3 device or a PCIE device and to switch between the USB3 controller and the PCIE controller based on the state of a USB3 select pin strap. Other embodiments are disclosed and claimed.