公开(公告)号：US10897364B2

公开(公告)日：2021-01-19

申请号：US15846045

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： Vivek De ,  Krishnan Ravichandran ,  Harish Krishnamurthy ,  Khondker Ahmed ,  Sriram Vangal ,  Vaibhav Vaidya ,  Turbo Majumder ,  Christopher Schaef ,  Suhwan Kim ,  Xiaosen Liu ,  Nachiket Desai

IPC: H04L9/32

Abstract: Spin Hall Effect (SHE) magneto junction memory cells (e.g., magnetic tunneling junction (MTJ) or spin valve based memory cells) are used to implement high entropy physically unclonable function (PUF) arrays utilizing stochastics interactions of both parameter variations of the SHE-MTJ structures as well as random thermal noises. An apparatus is provided which comprises: an array of PUF devices, wherein an individual device of the array comprises a magnetic junction and an interconnect, wherein the interconnect comprises a spin orbit coupling material; a circuitry to sense values stored in the array, and to provide an output; and a comparator to compare the output with a code.

公开(公告)号：US10205084B2

公开(公告)日：2019-02-12

申请号：US15087613

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Vaibhav Vaidya ,  Suhwan Kim

IPC: H02J7/00 ,  H01L41/113 ,  H02N2/18 ,  H02J7/34

Abstract: Techniques for harvesting electrical energy from a plurality of harvesters is disclosed. An example energy harvesting system includes a plurality of harvesters and a signal conditioning circuit selectively coupled to an output of each of the plurality of harvesters. The system also includes an energy storage element coupled to the output of the signal conditioning circuit to be charged by the plurality of harvesters through the signal conditioning circuit. The system also includes a controller to discharge a selected harvester to the signal conditioning circuit when an output of the selected harvester triggers a charge collection.

公开(公告)号：US11747371B2

公开(公告)日：2023-09-05

申请号：US17006715

申请日：2020-08-28

Applicant: Intel Corporation

Inventor： Nachiket Desai ,  Harish Krishnamurthy ,  Suhwan Kim ,  Fabrice Paillet

IPC: G01R19/00 ,  H03F1/34 ,  H03F3/45 ,  H02M3/158 ,  G01R1/30 ,  H03F1/42 ,  G05F3/26 ,  H02M1/00

CPC classification number: G01R19/0023 ,  G01R1/30 ,  G05F3/262 ,  H02M3/158 ,  H03F1/34 ,  H03F1/42 ,  H03F3/45748 ,  H02M1/0009 ,  H03F2203/45084

Abstract: A current sensing topology uses an amplifier with capacitively coupled inputs in feedback to sense the input offset of the amplifier, which can be compensated for during measurement. The amplifier with capacitively coupled inputs in feedback is used to: operate the amplifier in a region where the input common-mode specifications are relaxed, so that the feedback loop gain and/or bandwidth is higher; operate the sensor from the converter input voltage by employing high-PSRR (power supply rejection ratio) regulators to create a local, clean supply voltage, causing less disruption to the power grid in the switch area; sample the difference between the input voltage and the controller supply, and recreate that between the drain voltages of the power and replica switches; and compensate for power delivery network related (PDN-related) changes in the input voltage during current sensing.

公开(公告)号：US11658570B2

公开(公告)日：2023-05-23

申请号：US17009661

申请日：2020-09-01

Applicant: Intel Corporation

Inventor： Harish Krishnamurthy ,  Sheldon Weng ,  Nachiket Desai ,  Suhwan Kim ,  Fabrice Paillet

IPC: G06F1/00 ,  H02M3/157 ,  G06F1/26 ,  H02M3/158 ,  H03H17/02

CPC classification number: H02M3/157 ,  G06F1/26 ,  H02M3/1584 ,  H03H17/0211

Abstract: A digital control scheme controls an integrator of a PID filter to implement non-linear control of saturating the duty cycle during which the proportional and derivative terms of the PID filter are set to 0 while the integrator and its internal states (previous values or memory) is set to a duty cycle that is the sum of the current nominal duty cycle plus a deltaD. The deltaD is the maximum duty cycle increment that is used to regulate a voltage regulator from ICCmin to ICCmax and is a configuration register that can be set post silicon. An FSM moves from a non-linear all ON state to an open loop duty cycle which maintains the output voltage slightly higher than the required Vref. After a certain period in this open loop, the FSM then ramps down the open loop duty cycle value until the output voltage is close to the Vref.

公开(公告)号：US20200220457A1

公开(公告)日：2020-07-09

申请号：US16820555

申请日：2020-03-16

Applicant: Intel Corporation

Inventor： Lilly Huang ,  Christopher Schaef ,  Vaibhav Vaidya ,  Suhwan Kim

IPC: H02M3/07 ,  H02M3/158 ,  H02J7/34

Abstract: Apparatuses, methods and storage medium associated with deriving power output from an energy harvester are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a plurality of times at which an intermediate voltage of a two stage power conversion circuit corresponds to a voltage reference, and ascertain an amount of time between one of the identified times and another one of the identified times. The one or more processors, devices, and/or circuitry may derive a power or current value associated with the second power supply using the amount of time.

公开(公告)号：US10530254B2

公开(公告)日：2020-01-07

申请号：US15632086

申请日：2017-06-23

Applicant: INTEL CORPORATION

Inventor： Khondker Ahmed ,  Vivek De ,  Nachiket Desai ,  Suhwan Kim ,  Harish Krishnamurthy ,  Xiaosen Liu ,  Turbo Majumder ,  Krishnan Ravichandran ,  Christopher Schaef ,  Vaibhav Vaidya ,  Sriram Vangal

IPC: H02M3/158 ,  H02M1/08 ,  H02M1/00

Abstract: Embodiments described herein concern operating a peak-delivered-power (PDP) controller. Operating a PDP includes calculating the new power output value from the output voltage value and the output current value, determining whether the new power output value is greater than the previous power output value to determine whether the voltage regulator is outputting a maximum power output, based on a determination that the new power output value is greater than the previous power output value, providing an instruction to a duty generator to increase a duty cycle of the voltage regulator, based on a determination that the new power output value is not greater than the previous power output value, providing an instruction to the duty generator to decrease the duty cycle of the voltage regulator, and replacing the previous power output value with the new power output value.

公开(公告)号：US10379592B2

公开(公告)日：2019-08-13

申请号：US15462257

申请日：2017-03-17

Applicant: INTEL CORPORATION

Inventor： Dileep Kurian ,  Tanay Karnik ,  David Arditti Ilitzky ,  Ankit Gupta ,  Sriram Kabisthalam Muthukumar ,  Vaibhav Vaidya ,  Suhwan Kim ,  Christopher Schaef ,  Ilya Klochkov

IPC: G06F9/00 ,  G06F1/3212 ,  G06F1/3287 ,  G06F1/329

Abstract: The present disclosure provides for the management of power of a NZE IoT device. Managing power can include receiving the one or more asynchronous events from the asynchronous event system, determining if any of the one or more asynchronous events meet a respective charge qualification, generating the power-on command for the power-managed compute system if any of the one or more asynchronous events meet the respective charge qualification, and waiting for a power source to reach a threshold associated with the respective charge qualification if any of the one or more asynchronous events do not meet the respective charge qualification.

公开(公告)号：US20170271873A1

公开(公告)日：2017-09-21

申请号：US15076444

申请日：2016-03-21

Applicant: Intel Corporation

Inventor： Lilly Huang ,  Christopher Schaef ,  Vaibhav Vaidya ,  Suhwan Kim

IPC: H02J3/38 ,  H02M3/07

CPC classification number: H02M3/07 ,  H02J7/34 ,  H02M3/1582 ,  H02M2001/007

Abstract: Apparatuses, methods and storage medium associated with deriving power output from an energy harvester are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a plurality of times at which an intermediate voltage of a two stage power conversion circuit corresponds to a voltage reference, and ascertain an amount of time between one of the identified times and another one of the identified times. The one or more processors, devices, and/or circuitry may derive a power or current value associated with the second power supply using the amount of time.

公开(公告)号：US20220069810A1

公开(公告)日：2022-03-03

申请号：US17006726

申请日：2020-08-28

Applicant: Intel Corporation

Inventor： Nachiket Desai ,  Suhwan Kim ,  Harish Krishnamurthy ,  Christopher Schaef

IPC: H03K3/037 ,  H03K5/24 ,  H03K17/687

Abstract: A digital self-start controller, which is functional without fuse and/or trim information. The self-start controller protects a DC-DC converter against large inrush currents and voltage overshoots, while being capable of following a variable VID (voltage identification) reference ramp imposed by the system. The self-start controller uses a relaxation oscillator to set the switching frequency of the DC-DC converter. The oscillator can be initialized using either a clock or current reference to be close to a desired operating frequency. The output of the DC-DC converter is coupled weakly to the oscillator to set the duty cycle for closed loop operation. The controller is naturally biased such that the output supply voltage is always slightly higher than a set point, eliminating the need for any process, voltage, and/or temperature (PVT) imposed trims.

公开(公告)号：US11205962B2

公开(公告)日：2021-12-21

申请号：US16409562

申请日：2019-05-10

Applicant: Intel Corporation

Inventor： Nachiket Desai ,  Harish Krishnamurthy ,  Suhwan Kim

IPC: G06F1/26 ,  H02M1/14 ,  H02M3/158 ,  H02M3/157 ,  H02M3/15 ,  H02M1/00

Abstract: An apparatus is described which includes a delay-line with reasonably matched delay cells and some logic to ascertain both a correct number of DC-DC converters and interleaving angles or phase offsets. The apparatus measures an operating frequency in real-time in multiples of the individual delay cells of the delay-line. The smaller the period, the higher the load coupled to the DC-DC converters and, therefore the greater the number of DC-DC converters are needed to service the load. The period determines the load and can be used to determine the number of DC-DC converters needed and thereby accomplishing autonomous phase enabling/shedding.