公开(公告)号：US20170040793A1

公开(公告)日：2017-02-09

申请号：US15297086

申请日：2016-10-18

Applicant: Intel Corporation

Inventor： AKM AHSAN ,  Walid M. HAFEZ

IPC: H02H9/04 ,  H01L29/08 ,  H01L27/02 ,  H01L29/78

CPC classification number: H02H9/046 ,  H01L27/027 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/7851 ,  H01L2924/0002 ,  H02H3/22 ,  H01L2924/00

Abstract: Snapback ESD protection device employing one or more non-planar metal-oxide-semiconductor transistors (MOSFETs) are described. The ESD protection devices may further include lightly-doped extended drain regions, the resistances of which may be capacitively controlled through control gates independent of a gate electrode held at a ground potential. Control gates may be floated or biased to modulate ESD protection device performance. In embodiments, a plurality of core circuits are protected with a plurality of non-planar MOSFET-based ESD protection devices with control gate potentials varying across the plurality.

Abstract translation: 描述采用一个或多个非平面金属氧化物半导体晶体管（MOSFET）的Snapback ESD保护装置。 ESD保护器件还可以包括轻掺杂的延伸漏极区，其电阻可以通过独立于保持在接地电位的栅电极的控制栅电容地控制。 控制栅极可以浮置或偏置以调制ESD保护器件的性能。 在实施例中，多个核心电路被多个非平面的基于MOSFET的ESD保护器件保护，其中控制栅极电位在多个上变化。

公开(公告)号：US20170018658A1

公开(公告)日：2017-01-19

申请号：US15121879

申请日：2014-07-14

Applicant: Intel Corporation

Inventor： Walid M. HAFEZ ,  Chia-Hong JAN

IPC: H01L29/8605 ,  H01L29/66 ,  H01L29/808

CPC classification number: H01L29/0649 ,  H01L27/098 ,  H01L29/0657 ,  H01L29/404 ,  H01L29/66166 ,  H01L29/66803 ,  H01L29/66901 ,  H01L29/808 ,  H01L29/8605

Abstract: A solid source-diffused junction is described for fin-based electronics. In one example, a fin is formed on a substrate. A glass of a first dopant type is deposited over the substrate and over a lower portion of the fin. A glass of a second dopant type is deposited over the substrate and the fin. The glass is annealed to drive the dopants into the fin and the substrate. The glass is removed and a first and a second contact are formed over the fin without contacting the lower portion of the fin.

Abstract translation: 对于基于鳍的电子器件描述了固体源极扩散结。 在一个示例中，在基板上形成翅片。 第一掺杂剂类型的玻璃沉积在衬底上并且在鳍的下部上方。 在衬底和鳍上沉积一层第二掺杂剂类型。 将玻璃退火以将掺杂剂驱动到翅片和基底中。 去除玻璃并且在翅片之上形成第一和第二接触件，而不接触翅片的下部。

公开(公告)号：US20250089312A1

公开(公告)日：2025-03-13

申请号：US18244090

申请日：2023-09-08

Applicant: Intel Corporation

Inventor： Rahul RAMASWAMY ,  Marko RADOSAVLJEVIC ,  Walid M. HAFEZ ,  Hsu-Yu CHANG ,  Jeong Dong KIM ,  Scott MOKLER

IPC: H01L29/06 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Gate-all-around integrated circuit structures having differential nanowire thickness and gate oxide thickness, and methods of fabricating gate-all-around integrated circuit structures having differential nanowire thickness and gate oxide thickness, are described. For example, an integrated circuit structure includes a nanowire with an outer thickness and an inner thickness, the inner thickness less than the outer thickness. The nanowire tapers from outer regions having the outer thickness to an inner region having the inner thickness. A dielectric material is on and surrounding the nanowire such that a combined thickness of the nanowire and the dielectric material in the inner region is approximately the same as the outer thickness of the nanowire.

公开(公告)号：US20230420501A1

公开(公告)日：2023-12-28

申请号：US18244741

申请日：2023-09-11

Applicant: Intel Corporation

Inventor： Rahul RAMASWAMY ,  Walid M. HAFEZ ,  Tanuj TRIVEDI ,  Jeong Dong KIM ,  Ting CHANG ,  Babak FALLAHAZAD ,  Hsu-Yu CHANG ,  Nidhi NIDHI

IPC: H01L29/06 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/423

CPC classification number: H01L29/0669 ,  H01L29/785 ,  H01L27/0924 ,  H01L21/823821 ,  H01L21/823814 ,  H01L29/42392 ,  B82Y40/00

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a substrate, and a first transistor of a first conductivity type over the substrate. In an embodiment, the first transistor comprises a first semiconductor channel, and a first gate electrode around the first semiconductor channel. In an embodiment, the semiconductor device further comprises a second transistor of a second conductivity type above the first transistor. The second transistor comprises a second semiconductor channel, and a second gate electrode around the second semiconductor channel. In an embodiment, the second gate electrode and the first gate electrode comprise different materials.

公开(公告)号：US20230207569A1

公开(公告)日：2023-06-29

申请号：US18111313

申请日：2023-02-17

Applicant: Intel Corporation

Inventor： Walid M. HAFEZ ,  Jeng-Ya D. YEH ,  Curtis TSAI ,  Joodong PARK ,  Chia-Hong JAN ,  Gopinath BHIMARASETTI

IPC: H01L27/12 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  H01L29/423

CPC classification number: H01L27/1211 ,  H01L21/823468 ,  H01L21/845 ,  H01L29/66545 ,  H01L21/02532 ,  H01L21/02598 ,  H01L21/28158 ,  H01L29/6681 ,  H01L29/51 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/823437 ,  H01L29/513 ,  H01L29/42356 ,  H01L21/0228 ,  H01L21/02164 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/6656

Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.

公开(公告)号：US20220130962A1

公开(公告)日：2022-04-28

申请号：US17569376

申请日：2022-01-05

Applicant: Intel Corporation

Inventor： Gopinath BHIMARASETTI ,  Walid M. HAFEZ ,  Joodong PARK ,  Weimin HAN ,  Raymond E. COTNER ,  Chia-Hong JAN

IPC: H01L29/36 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088

Abstract: Non-planar semiconductor devices having omega-fins with doped sub-fin regions and methods of fabricating non-planar semiconductor devices having omega-fins with doped sub-fin regions are described. For example, a semiconductor device includes a plurality of semiconductor fins disposed above a semiconductor substrate, each semiconductor fin having a sub-fin portion below a protruding portion, the sub-fin portion narrower than the protruding portion. A solid state dopant source layer is disposed above the semiconductor substrate, conformal with the sub-fin region but not the protruding portion of each of the plurality of semiconductor fins. An isolation layer is disposed above the solid state dopant source layer and between the sub-fin regions of the plurality of semiconductor fins. A gate stack is disposed above the isolation layer and conformal with the protruding portions of each of the plurality of semiconductor fins.

公开(公告)号：US20220130871A1

公开(公告)日：2022-04-28

申请号：US17568652

申请日：2022-01-04

Applicant: Intel Corporation

Inventor： Walid M. HAFEZ ,  Jeng-Ya D. YEH ,  Curtis TSAI ,  Joodong PARK ,  Chia-Hong JAN ,  Gopinath BHIMARASETTI

IPC: H01L27/12 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51

Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.

公开(公告)号：US20220093588A1

公开(公告)日：2022-03-24

申请号：US17026040

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Sairam SUBRAMANIAN ,  Walid M. HAFEZ ,  Hsu-Yu CHANG ,  Chia-Hong JAN ,  Tanuj TRIVEDI

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/786 ,  H01L29/423 ,  H01L21/8234

Abstract: Adjacent gate-all-around integrated circuit structures having non-merged epitaxial source or drain regions, and methods of fabricating adjacent gate-all-around integrated circuit structures having non-merged epitaxial source or drain regions, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate. One or more gate stacks is over the first and second vertical arrangements of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening dielectric structure is between adjacent ones of the first epitaxial source or drain structures and between adjacent ones of the second epitaxial source or drain structures.

公开(公告)号：US20210184001A1

公开(公告)日：2021-06-17

申请号：US16713684

申请日：2019-12-13

Applicant: Intel Corporation

Inventor： Tanuj TRIVEDI ,  Rahul RAMASWAMY ,  Jeong Dong KIM ,  Ting CHANG ,  Walid M. HAFEZ ,  Babak FALLAHAZAD ,  Hsu-Yu CHANG ,  Nidhi NIDHI

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/78 ,  H01L27/088 ,  H01L29/66

Abstract: Embodiments disclosed herein include nanowire and nanoribbon devices with non-uniform dielectric thicknesses. In an embodiment, the semiconductor device comprises a substrate and a plurality of first semiconductor layers in a vertical stack over the substrate. The first semiconductor layers may have a first spacing. In an embodiment, a first dielectric surrounds each of the first semiconductor layers, and the first dielectric has a first thickness. The semiconductor device may further comprise a plurality of second semiconductor layers in a vertical stack over the substrate, where the second semiconductor layers have a second spacing that is greater than the first spacing. In an embodiment a second dielectric surrounds each of the second semiconductor layers, and the second dielectric has a second thickness that is greater than the first thickness.

公开(公告)号：US20210090956A1

公开(公告)日：2021-03-25

申请号：US17112959

申请日：2020-12-04

Applicant: Intel Corporation

Inventor： Roman W. OLAC-VAW ,  Walid M. HAFEZ ,  Chia-Hong JAN ,  Pei-Chi LIU

IPC: H01L21/8234 ,  H01L27/12 ,  H01L21/84 ,  H01L29/78 ,  H01L21/28 ,  H01L23/528 ,  H01L27/088 ,  H01L29/49 ,  H01L21/8238

Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.