公开(公告)号：US20210165712A1

公开(公告)日：2021-06-03

申请号：US17171430

申请日：2021-02-09

Applicant: Intel Corporation

Inventor： Debarnab Mitra ,  Zion S. Kwok ,  Ravi H. Motwani

IPC: G06F11/10 ,  H03M13/11

Abstract: An embodiment of an electronic apparatus comprises one or more substrates, and logic coupled to the one or more substrates, the logic to detect unreliable messages between check nodes and variable nodes in association with an error correction operation, determine respective degrees of unreliability for the unreliable messages, and reduce an influence of the unreliable messages on the error correction operation, as compared to an influence of reliable messages between the check nodes and the variables nodes, based on the determined respective degrees of unreliability. Other embodiments are disclosed and claimed.

公开(公告)号：US10804935B2

公开(公告)日：2020-10-13

申请号：US15860513

申请日：2018-01-02

Applicant: Intel Corporation

Inventor： Zion S. Kwok

IPC: H03M13/00 ,  G11C29/00 ,  H03M13/15 ,  H03M13/37

Abstract: Devices, systems, and methods that reduce the latency of detecting that a codeword is uncorrectable are disclosed and described. Such devices, systems, and methods allow the determination that a codeword is uncorrectable prior to determining error locations in the codeword, thus eliminating the need for such an error location search.

公开(公告)号：US10250278B2

公开(公告)日：2019-04-02

申请号：US14977292

申请日：2015-12-21

Applicant: INTEL CORPORATION

Inventor： Zion S. Kwok

IPC: H03M7/30

Abstract: These present disclosure provides devices and techniques to compress a list of integers. A circuit may include a sorter to sort a list of integers and a subtractor to determine a range of integers represented in the list and to recursively subdivide the range into sub-ranges. The circuit may also include a bit determiner to determine an amount of information (e.g., bits) to use to add indications of the integers in the list to a compresses list information element based on the range and the sub-ranges.

公开(公告)号：US10176042B2

公开(公告)日：2019-01-08

申请号：US15438655

申请日：2017-02-21

Applicant: INTEL CORPORATION

Inventor： Andre Lei ,  Scott Nelson ,  Zion S. Kwok ,  Ravi H. Motwani

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/11 ,  G11C5/14

Abstract: Provided are a method, system, and apparatus using reliability information from multiple storage units and a parity storage unit to recover data for a failed one of the storage units. A decoding operation of the codeword is performed in each of the storage units comprising the data storage units other than the target data storage unit and the parity storage unit to produce reliability information. In response to the decoding operation failing for at least one additional failed storage unit comprising the data and/or parity storage units other than the target data storage unit that failed to decode, reliability information is obtained for the data portion of the at least one additional failed storage unit. The reliability information obtained from the storage units other than the target data storage unit is used to produce corrected data for the data unit in the target data storage unit.

公开(公告)号：US10163471B2

公开(公告)日：2018-12-25

申请号：US15474659

申请日：2017-03-30

Applicant: INTEL CORPORATION

Inventor： Zion S. Kwok

IPC: G11C7/22

Abstract: A memory controller circuitry includes a timestamp circuitry and a demarcation voltage (VDM) selection circuitry. The timestamp circuitry is to capture a global timer index from a global timer having a granularity, G. The timestamp circuitry is further to fetch a timestamp for a memory block that includes a group of sub-blocks that includes a target sub-block. The demarcation voltage (VDM) selection circuitry is to fetch a combined count from a count store. The combined count represents a combined state. The combined state includes a target individual state of the target sub-block and a respective individual state of each of at least one other sub-block of the group of sub-blocks included in the memory block.

公开(公告)号：US09054742B2

公开(公告)日：2015-06-09

申请号：US13829907

申请日：2013-03-14

Applicant: Intel Corporation

Inventor： Zion S. Kwok

IPC: H03M13/00 ,  H03M13/15

CPC classification number: H03M13/1515 ,  H03M13/153 ,  H03M13/154 ,  H03M13/159

Abstract: A codeword may have errors and erasures. In embodiments, an apparatus may include a syndrome calculator configured to generate partial syndromes of the codeword, an erasure locator configured to generate an erasure locator polynomial, and a syndrome modifier configured to generate modified partial syndromes based at least in part on the partial syndromes and the erasure locator polynomial. The apparatus may further include an error locator configured to generate an error locator polynomial using the modified partial syndromes, for error and erasure decoding of the codeword.

Abstract translation: 码字可能有错误和擦除。 在实施例中，装置可以包括：校正子计算器，被配置为生成码字的部分综合征，被配置为生成擦除定位多项式的擦除定位器，以及校正子修改器，被配置为至少部分地基于部分综合征产生修改的部分综合征， 擦除定位多项式。 该装置还可以包括错误定位器，该错误定位器被配置为使用修改的部分校正子来生成错误定位器多项式，用于对码字的错误和擦除解码。

公开(公告)号：US20190102320A1

公开(公告)日：2019-04-04

申请号：US15721379

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Philip Hillier ,  Jeffrey W. Ryden ,  Muthukumar P. Swaminathan ,  Zion S. Kwok ,  Kunal A. Khochare ,  Richard P. Mangold ,  Prashant S. Damle

IPC: G06F12/126 ,  G06F12/02 ,  G11C7/22

Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller memory; a timestamp circuitry and a demarcation voltage (VDM) selection circuitry. The timestamp circuitry is to capture a current timer index from a timer circuitry in response to an initiation of a periodic patrol scrub and to compare the current timer index to a stored timestamp. The VDM selection circuitry is to update a state of a sub-block of a memory array, if the state is less than a threshold and a difference between the current timer index and the stored timestamp is nonzero. The timestamp circuitry is further to store the current timer index as a new timestamp.

公开(公告)号：US09697140B2

公开(公告)日：2017-07-04

申请号：US14493924

申请日：2014-09-23

Applicant: Intel Corporation

Inventor： Zion S. Kwok

IPC: G06F12/14 ,  G06F21/80 ,  G06F21/79

CPC classification number: G06F12/1408 ,  G06F21/79 ,  G06F2212/402 ,  G06F2212/403

Abstract: Apparatus, systems, and methods for AES integrity check in memory are described. In one embodiment, a controller comprises logic to receive a write request from a host device to write a line of data to the memory device, determine a first plaintext cyclic redundancy check from the line of data, encrypt the line of data, encrypt the first plaintext CRC with a unique value to generate a first encrypted CRC, and store the encrypted line of data and the first encrypted CRC in memory. Other embodiments are also disclosed and claimed.

公开(公告)号：US09691492B1

公开(公告)日：2017-06-27

申请号：US15280669

申请日：2016-09-29

Applicant: INTEL CORPORATION

Inventor： Bruce Querbach ,  Zion S. Kwok ,  Christopher F. Connor ,  Philip Hillier ,  Jeffrey W. Ryden

IPC: G11C5/14 ,  G11C16/28 ,  G11C16/10 ,  G11C16/30

CPC classification number: G11C16/28 ,  G11C16/10 ,  G11C16/20 ,  G11C16/30

Abstract: A predetermined pattern of bits is written to a non-volatile memory device prior to powering down the non-volatile memory device. A plurality of voltages are applied to the non-volatile memory device to determine which voltage of the plurality of voltages allows the predetermined pattern of bits to be read with a least amount of error. The determined voltage is set to be a demarcation voltage for reading from the non-volatile memory device.

公开(公告)号：US09588841B2

公开(公告)日：2017-03-07

申请号：US14499078

申请日：2014-09-26

Applicant: INTEL CORPORATION

Inventor： Andre Lei ,  Scott Nelson ,  Zion S. Kwok ,  Ravi H. Motwani

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/11 ,  G11C5/14

CPC classification number: G06F11/1068 ,  G06F11/1012 ,  G11C5/143 ,  G11C29/52 ,  H03M13/1105

Abstract: Provided are a method, system, and apparatus using reliability information from multiple storage units and a parity storage unit to recover data for a failed one of the storage units. A decoding operation of the codeword is performed in each of the storage units comprising the data storage units other than the target data storage unit and the parity storage unit to produce reliability information. In response to the decoding operation failing for at least one additional failed storage unit comprising the data and/or parity storage units other than the target data storage unit that failed to decode, reliability information is obtained for the data portion of the at least one additional failed storage unit. The reliability information obtained from the storage units other than the target data storage unit is used to produce corrected data for the data unit in the target data storage unit.

Abstract translation: 提供了使用来自多个存储单元的可靠性信息和奇偶校验存储单元来恢复存储单元中的一个故障存储单元的数据的方法，系统和装置。 在包括目标数据存储单元和奇偶校验存储单元以外的数据存储单元的每个存储单元中执行码字的解码操作，以产生可靠性信息。 响应于对于至少一个附加的故障存储单元的解码操作失败，所述至少一个附加故障存储单元包括除了解码失败的目标数据存储单元之外的数据和/或奇偶校验存储单元，对于至少一个附加的数据部分的数据部分获得可靠性信息 存储单元故障 从目标数据存储单元以外的存储单元获得的可靠性信息用于生成目标数据存储单元中的数据单元的校正数据。