公开(公告)号：US20190189776A1

公开(公告)日：2019-06-20

申请号：US15844950

申请日：2017-12-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： ROBIN HSIN KUO CHAO ,  CHOONGHYUN LEE ,  HENG WU ,  CHUN WING YEUNG ,  JINGYUN Zhang

IPC: H01L29/66 ,  H01L29/10 ,  H01L21/306 ,  H01L21/8234

CPC classification number: H01L29/66598 ,  H01L21/30604 ,  H01L21/823431 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/66795

Abstract: A semiconductor device includes a first nanosheet stack, a second nanosheet stack, and a third nanosheet stack arranged on a substrate. The semiconductor device includes a gate arranged on the first nanosheet stack, the second nanosheet stack, and the third nanosheet stack. The semiconductor device includes a channel extending through the gate and from the first nanosheet stack, the second nanosheet stack, and to the third nanosheet stack in a serpentine fashion. The semiconductor device includes a first source/drain and a second source/drain arranged on opposing sides of the gate.

公开(公告)号：US20180204839A1

公开(公告)日：2018-07-19

申请号：US15406985

申请日：2017-01-16

Applicant: International Business Machines Corporation

Inventor： RUQIANG BAO ,  HEMANTH JAGANNATHAN ,  PAUL JAMISON ,  CHOONGHYUN LEE ,  VIJAY NARAYANAN

IPC: H01L27/092 ,  H01L29/49 ,  H01L21/8234 ,  H01L29/51

CPC classification number: H01L27/0924 ,  H01L21/823431 ,  H01L21/823437 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66666 ,  H01L29/7827

Abstract: A semiconductor device is provided and has an n-channel field effect transistor (nFET) bottom junction and a p-channel field effect transistor (pFET) bottom junction. The semiconductor device includes first and second fin formations operably disposed in the nFET and pFET bottom junctions, respectively. The semiconductor device can also include an nFET metal gate layer deposited for oxygen absorption onto a high-k dielectric layer provided about the first fin formation in the nFET bottom junction and onto a pFET metal gate layer provided about the second fin formation in the pFET bottom junction. Alternatively, the semiconductor device can include an oxygen scavenging layer deposited onto the pFET metal gate layer about the second fin formation in the pFET bottom junction and, with the pFET metal gate layer deposited onto the nFET metal gate layer about the first fin formation in the nFET bottom junction, onto the pFET metal gate layer in the nFET bottom junction.

公开(公告)号：US20230189496A1

公开(公告)日：2023-06-15

申请号：US17644076

申请日：2021-12-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： CHOONGHYUN LEE ,  TAKASHI ANDO ,  JINGYUN ZHANG ,  ALEXANDER REZNICEK

IPC: H01L27/11 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L27/1108 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/0649 ,  H01L29/78696

Abstract: A semiconductor device is provided. The semiconductor device includes a first device including a first nanosheet stack formed on a substrate, the first nanosheet stack including alternating layers of a first work function metal (WFM) gate layer and an active semiconductor layer, a second nanosheet stack formed on the substrate, the second nanosheet stack including alternating layers of a second WFM gate layer and the active semiconductor layer, a shallow trench isolation (STI) region formed in the substrate between the first nanosheet stack and the second nanosheet stack, and an STI divot formed in the STI region. The first WFM gate layer of the first nanosheet stack is formed in the STI divot.

公开(公告)号：US20190252520A1

公开(公告)日：2019-08-15

申请号：US16391826

申请日：2019-04-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： ROBIN HSIN KUO CHAO ,  CHOONGHYUN LEE ,  HENG WU ,  CHUN WING YEUNG ,  JINGYUN Zhang

IPC: H01L29/66 ,  H01L21/306 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/10

CPC classification number: H01L29/66598 ,  H01L21/30604 ,  H01L21/823431 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/66795

Abstract: A semiconductor device includes a first nanosheet stack, a second nanosheet stack, and a third nanosheet stack arranged on a substrate. The semiconductor device includes a gate arranged on the first nanosheet stack, the second nanosheet stack, and the third nanosheet stack. The semiconductor device includes a channel extending through the gate and from the first nanosheet stack, the second nanosheet stack, and to the third nanosheet stack in a serpentine fashion. The semiconductor device includes a first source/drain and a second source/drain arranged on opposing sides of the gate.

公开(公告)号：US20190214459A1

公开(公告)日：2019-07-11

申请号：US15868003

申请日：2018-01-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： KANGGUO CHENG ,  CHOONGHYUN LEE ,  JUNTAO LI ,  PENG XU

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/423

Abstract: A sacrificial gate stack for forming a nanosheet transistor includes a substrate. first, second and third silicon channel nanosheets formed over the substrate, and a first sandwich of germanium (Ge) containing layers disposed between the substrate and first silicon channel nanosheet. The stack also includes a second sandwich of Ge containing layers disposed between the first silicon channel nanosheet and the second silicon channel nanosheet; and a third sandwich of Ge containing layers disposed between the second silicon channel nanosheet and the third silicon channel nanosheet. Each sandwich includes first and second low Ge containing layers surrounding a silicon germanium (SiGe) sacrificial nanosheet that has a higher Ge concentration than the first and second low Ge containing layers.

公开(公告)号：US20190181051A1

公开(公告)日：2019-06-13

申请号：US16267479

申请日：2019-02-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Brent A. Anderson ,  RUQIANG BAO ,  Kangguo Cheng ,  HEMANTH JAGANNATHAN ,  CHOONGHYUN LEE ,  JUNLI WANG

IPC: H01L21/8238 ,  H01L29/08 ,  H01L29/06 ,  H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L23/535

Abstract: Forming a PFET work function metal layer on a p-type field effect transistor (PFET) fin in a PFET region and on an n-type field effect transistor (NFET) fin in an NFET region, removing a portion of the PFET work function metal layer between the PFET fin and the NFET fin, thinning the PFET work function metal layer, patterning an organic planarization layer on the PFET work function metal layer, where the organic planarization layer covers the PFET region and partially covers the NFET region, removing the PFET work function metal layer in the NFET region, by etching isotropically selective to the organic planarization layer and an insulator in the NFET region, removing the organic planarization layer, and conformally forming an NFET work function metal layer on the semiconductor structure.

公开(公告)号：US20190165128A1

公开(公告)日：2019-05-30

申请号：US16100317

申请日：2018-08-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： SEYOUNG KIM ,  CHOONGHYUN LEE ,  INJO OK ,  SOON-CHEON SEO

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/10 ,  H01L29/737 ,  H01L29/732 ,  H01L21/324 ,  H01L21/308 ,  H01L21/306 ,  H01L29/165

CPC classification number: H01L29/66242 ,  H01L21/02112 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/324 ,  H01L29/0684 ,  H01L29/0817 ,  H01L29/1004 ,  H01L29/165 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/737 ,  H01L29/7371 ,  H01L29/7378 ,  H01L2924/1305

Abstract: A method of manufacturing a bipolar junction transistor (BJT) structure is provided. Pattern etching through a second semiconductor layer and recessing a silicon germanium layer are performed to form a plurality of vertical fins each including a silicon germanium pattern, a second semiconductor pattern and a hard mask pattern sequentially stacked on a first semiconductor layer above a substrate. First spacers are formed on sidewalls of the plurality of vertical fins. Exposed silicon germanium layer above the first semiconductor layer is directionally etched away. A germanium oxide layer is conformally coated to cover all exposed top and sidewall surfaces. Condensation annealing followed by silicon oxide strip is performed. The first spacers, remaining germanium oxide layer and the hard mask pattern are removed. A dielectric material is deposited to isolate the plurality of vertical fins. An emitter, a base and a collector contacts are formed to connect to the second semiconductor pattern, the silicon germanium pattern and the first semiconductor layer, respectively. The BJT structures manufactured are also provided.