公开(公告)号：US20170154961A1

公开(公告)日：2017-06-01

申请号：US15154606

申请日：2016-05-13

Applicant: International Business Machines Corporation

Inventor： KARTHIK BALAKRISHNAN ,  KANGGUO CHENG ,  POUYA HASHEMI ,  ALEXANDER REZNICEK

IPC: H01L29/06 ,  H01L21/308 ,  H01L21/324 ,  H01L29/165 ,  H01L21/02

CPC classification number: H01L21/02694 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/28255 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/32055 ,  H01L21/324 ,  H01L21/7624 ,  H01L21/76264 ,  H01L21/76283 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/267 ,  H01L29/7378 ,  H01L29/7848 ,  H01L29/785 ,  H01L31/1816 ,  H01L2924/10271

Abstract: A semiconductor device comprising a substrate having a region protruding from the substrate surface; a relaxed semiconductor disposed on the region; an additional semiconductor disposed on the relaxed semiconductor; and low density dielectric disposed next to and at least partially underneath the relaxed semiconductor and adjacent to the protruding region of the substrate.

公开(公告)号：US20160315144A1

公开(公告)日：2016-10-27

申请号：US15203847

申请日：2016-07-07

Applicant: International Business Machines Corporation

Inventor： KANGGUO CHENG ,  BALASUBRAMANIAN PRANATHARTHIHARAN ,  ALEXANDER REZNICEK ,  CHARAN V. SURISETTY

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/423

CPC classification number: H01L27/0886 ,  H01L21/28035 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7855

Abstract: The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs). In an embodiment, a dielectric region may be formed in a middle portion of a gate structure. The gate structure be formed using a gate replacement process, and may cover a middle portion of a first fin group, a middle portion of a second fin group and an intermediate region of the substrate between the first fin group and the second fin group. The dielectric region may be surrounded by the gate structure in the intermediate region. The gate structure and the dielectric region may physically separate epitaxial regions formed on the first fin group and the second fin group from one another.

公开(公告)号：US20150054032A1

公开(公告)日：2015-02-26

申请号：US14518590

申请日：2014-10-20

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： NICOLAS LOUBET ,  DOUGLAS LATULIPE ,  ALEXANDER REZNICEK

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/417 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/823425 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/4958 ,  H01L29/66628 ,  H01L29/66636

Abstract: A method for making a semiconductor device includes forming at least one gate stack on a layer comprising a first semiconductor material and etching source and drain recesses adjacent the at least one gate stack. The method further includes shaping the source and drain recesses to have a vertical side extending upwardly from a bottom to an inclined extension adjacent the at least one gate stack.

Abstract translation: 制造半导体器件的方法包括在包括第一半导体材料的层上形成至少一个栅极堆叠，以及邻近所述至少一个栅极堆叠的蚀刻源极和漏极凹陷。 该方法进一步包括成形源极和漏极凹槽以具有从底部向上延伸到与所述至少一个栅极堆叠相邻的倾斜延伸部的垂直侧。

公开(公告)号：US20180323288A1

公开(公告)日：2018-11-08

申请号：US16030359

申请日：2018-07-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： KANGGUO CHENG ,  RAMACHANDRA DIVAKARUNI ,  ALI KHAKIFIROOZ ,  ALEXANDER REZNICEK ,  SOON-CHEON SEO

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L29/161 ,  H01L29/16 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/66795 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device is provided that includes a pedestal of an insulating material present over at least one layer of a semiconductor material, and at least one fin structure in contact with the pedestal of the insulating material. Source and drain region structures are present on opposing sides of the at least one fin structure. At least one of the source and drain region structures includes at least two epitaxial material layers. A first epitaxial material layer is in contact with the at least one layer of semiconductor material. A second epitaxial material layer is in contact with the at least one fin structure. The first epitaxial material layer is separated from the at least one fin structure by the second epitaxial material layer. A gate structure present on the at least one fin structure.

公开(公告)号：US20170154982A1

公开(公告)日：2017-06-01

申请号：US15432320

申请日：2017-02-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： KANGGUO CHENG ,  RAMACHANDRA DIVAKARUNI ,  ALI KHAKIFIROOZ ,  ALEXANDER REZNICEK ,  SOON-CHEON SEO

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device is provided that includes a pedestal of an insulating material present over at least one layer of a semiconductor material, and at least one fin structure in contact with the pedestal of the insulating material. Source and drain region structures are present on opposing sides of the at least one fin structure. At least one of the source and drain region structures includes at least two epitaxial material layers. A first epitaxial material layer is in contact with the at least one layer of semiconductor material. A second epitaxial material layer is in contact with the at least one fin structure. The first epitaxial material layer is separated from the at least one fin structure by the second epitaxial material layer. A gate structure present on the at least one fin structure.

公开(公告)号：US20150247259A1

公开(公告)日：2015-09-03

申请号：US14711403

申请日：2015-05-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： BAHMAN HEKMATSHOAR-TABARI ,  ALI KHAKIFIROOZ ,  ALEXANDER REZNICEK ,  DEVENDRA K. SADANA ,  GHAVAM G. SHAHIDI ,  DAVOOD SHAHRJERDI

IPC: C30B25/18 ,  C30B29/06 ,  C30B25/10

Abstract: An epitaxy method includes providing an exposed crystalline region of a substrate material. Silicon is epitaxially deposited on the substrate material in a low temperature process wherein a deposition temperature is less than 500 degrees Celsius. A source gas is diluted with a dilution gas with a gas ratio of dilution gas to source gas of less than 1000.

Abstract translation: 外延生长方法包括提供衬底材料的暴露的结晶区域。 硅在低温工艺中外延沉积在衬底材料上，其中淀积温度低于500摄氏度。 源气体用稀释气体稀释，稀释气体与原料气体的气体比小于1000。

公开(公告)号：US20230189496A1

公开(公告)日：2023-06-15

申请号：US17644076

申请日：2021-12-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： CHOONGHYUN LEE ,  TAKASHI ANDO ,  JINGYUN ZHANG ,  ALEXANDER REZNICEK

IPC: H01L27/11 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L27/1108 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/0649 ,  H01L29/78696

Abstract: A semiconductor device is provided. The semiconductor device includes a first device including a first nanosheet stack formed on a substrate, the first nanosheet stack including alternating layers of a first work function metal (WFM) gate layer and an active semiconductor layer, a second nanosheet stack formed on the substrate, the second nanosheet stack including alternating layers of a second WFM gate layer and the active semiconductor layer, a shallow trench isolation (STI) region formed in the substrate between the first nanosheet stack and the second nanosheet stack, and an STI divot formed in the STI region. The first WFM gate layer of the first nanosheet stack is formed in the STI divot.

公开(公告)号：US20180190794A1

公开(公告)日：2018-07-05

申请号：US15897706

申请日：2018-02-15

Applicant: International Business Machines Corporation

Inventor： OLEG GLUSCHENKOV ,  SANJAY C. MEHTA ,  SHOGO MOCHIZUKI ,  ALEXANDER REZNICEK

IPC: H01L29/66 ,  H01L21/311

CPC classification number: H01L29/66666 ,  H01L21/31111 ,  H01L29/0847 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66795

Abstract: A method of forming a spacer for a vertical transistor is provided. The method includes forming a fin structure on a substrate, depositing a first spacer on exposed surfaces of the substrate to define gaps between the first spacer and the fin structure and depositing a second spacer on the exposed surfaces of the substrate in at least the gaps.

公开(公告)号：US20150303251A1

公开(公告)日：2015-10-22

申请号：US14732705

申请日：2015-06-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： KANGGUO CHENG ,  POUYA HASHEMI ,  ALI KHAKIFIROOZ ,  ALEXANDER REZNICEK

IPC: H01L29/06 ,  H01L29/22 ,  H01L29/267 ,  H01L29/205

CPC classification number: H01L29/0649 ,  H01L21/02002 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02463 ,  H01L21/0251 ,  H01L21/02546 ,  H01L21/02565 ,  H01L21/76251 ,  H01L21/76254 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/22 ,  H01L29/267

Abstract: A structure includes a handle substrate and an epitaxial oxide layer. The epitaxial oxide layer is bonded directly or indirectly to the handle substrate. Also included is a compound semiconductor layer adjoining and lattice matched to the epitaxial oxide layer.

Abstract translation: 一种结构包括手柄基板和外延氧化物层。 外延氧化物层直接或间接地结合到处理衬底上。 还包括与外延氧化物层相邻并晶格匹配的化合物半导体层。

公开(公告)号：US20150214117A1

公开(公告)日：2015-07-30

申请号：US14678024

申请日：2015-04-03

Applicant: International Business Machines Corporation

Inventor： KANGGUO CHENG ,  ALI KHAKIFIROOZ ,  ALEXANDER REZNICEK ,  GHAVAM G. SHAHIDI

IPC: H01L21/8238 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L21/823807 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/033 ,  H01L21/2018 ,  H01L21/2053 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/16 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7855

Abstract: Silicon and silicon germanium fins are formed on a semiconductor wafer or other substrate in a manner that facilitates production of closely spaced nFET and pFET devices. A patterned mandrel layer is employed for forming one or more recesses in the wafer prior to the epitaxial growth of a silicon germanium layer that fills the recess. Spacers are formed on the side walls of the patterned mandrel layer followed by removal of the mandrel layer. The exposed areas of the wafer and silicon germanium layer between the spacers are etched to form fins usable for nFET devices from the wafer and fins usable for pFET devices from the silicon germanium layer.