公开(公告)号：US20190123167A1

公开(公告)日：2019-04-25

申请号：US16216356

申请日：2018-12-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Cheng Chi ,  Ruilong Xie

IPC: H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/285 ,  H01L21/3105 ,  H01L29/06

Abstract: A method is presented for forming equal thickness gate spacers for a CMOS (complementary metal oxide semiconductor) device, the method includes forming a PFET (p-type field effect transistor) device and an NFET (n-type field effect transistor) device each including gate masks formed over dummy gates, forming PFET epi growth regions between the dummy gates of the PFET device, forming NFET epi growth regions between the dummy gates of the NFET device, depositing a nitride liner and an oxide over the PFET and NFET epi growth regions, the nitride liner and oxide extending up to the gate masks, and removing the dummy gates and the gate masks to form HKMGs (high-k metal gates) between the PFET and NFET epi growth regions.

公开(公告)号：US20180269320A1

公开(公告)日：2018-09-20

申请号：US15462175

申请日：2017-03-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Cheng Chi ,  Tenko Yamashita ,  Chen Zhang

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/161 ,  H01L29/10 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66

Abstract: A method of forming a vertical transport fin field effect transistor and a long-channel field effect transistor on the same substrate, including, forming a recessed region in a substrate and a fin region adjacent to the recessed region, forming one or more vertical fins on the fin region, forming a long-channel pillar from the substrate in the recessed region, where the long-channel pillar is at a different elevation than the one or more vertical fins, forming two or more long-channel source/drain plugs on the long-channel pillar, forming a bottom source/drain plug in the fin region, where the bottom source/drain plug is below the one or more vertical fins, forming a gate structure on the long-channel pillar and a gate structure on the one or more vertical fins, and forming a top source/drain on the top surface of the one or more vertical fins.

公开(公告)号：US20180005901A1

公开(公告)日：2018-01-04

申请号：US15196371

申请日：2016-06-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc.

Inventor： Cheng Chi ,  Ruilong Xie

IPC: H01L21/8238 ,  H01L23/522 ,  H01L29/417 ,  H01L23/528 ,  H01L23/485 ,  H01L21/311 ,  H01L29/66 ,  H01L27/12

CPC classification number: H01L23/5226 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/4855 ,  H01L23/5283 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/66545

Abstract: A method for forming a semiconductor device comprises forming a gate stack on a channel region of a semiconductor, forming a source/drain region adjacent to the channel region, depositing a first insulator layer over the source/drain region, and removing a portion of the first insulator layer to form a first cavity that exposes a portion of the source/drain region. A first conductive material is deposited in the first cavity, and a conductive extension is formed from the first conductive material over the first insulator layer. A protective layer is deposited over the extension and a second insulator layer is deposited over the protective layer. A portion of the second insulator layer is removed to form a second cavity that exposes the protective layer, and an exposed portion of the protective layer is removed to expose a portion of the extension. A second conductive material is deposited in the second cavity.

公开(公告)号：US20170294347A1

公开(公告)日：2017-10-12

申请号：US15096818

申请日：2016-04-12

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Cheng Chi ,  Ruilong Xie

IPC: H01L21/768 ,  H01L29/45 ,  H01L29/417 ,  H01L29/06 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/76897 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53257 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/41766 ,  H01L29/45

Abstract: Techniques relate to contacts for semiconductors. First gate contacts are formed on top of first gates, second gate contacts are on second gates, and terminal contacts are on silicide contacts. First gate contacts and terminal contacts are recessed to form a metal layer on top. Second gate contacts are recessed to be separately on each of the second gates. Filling material is formed on top of the recessed second gate contacts and metal layer. An upper layer is on top of the filling material. First metal vias are formed through filling and upper layers down to metal layer over first gate contacts. Second metal vias are formed through filling and upper layers down to metal layer over terminal contacts. Third metal vias are formed through filling and upper layers down to recessed second gate contacts over second gates. Third metal vias are taller than first.

公开(公告)号：US20160358820A1

公开(公告)日：2016-12-08

申请号：US15239178

申请日：2016-08-17

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES, INC. ,  STMicroelectronics, Inc.

Inventor： Shyng-Tsong Chen ,  Cheng Chi ,  Chi-Chun Liu ,  Sylvie M. Mignot ,  Yann A. Mignot ,  Hosadurga K. Shobha ,  Terry A. Spooner ,  Wenhui Wang ,  Yongan Xu

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76897 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329

Abstract: A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using a sidewall image transfer process. A dielectric layer is formed over the pillar and the underlying layer; and a via mask patterned over the dielectric layer, the via mask having a mask opening at least partially overlapping the pillar. A via opening is etched in the dielectric layer using the via mask, the mask opening defining a first lateral dimension of the via opening in a first direction and the pillar defining a second lateral dimension of the via opening in a second direction different than the first direction. The via opening is filled with a conductor to form the via. A semiconductor device and via structure are also provided.

Abstract translation: 提供了形成通孔到半导体器件的下层的方法。 该方法可以包括使用侧壁图像转移过程在下层上形成柱。 介电层形成在柱和下层之上; 以及图案化在所述电介质层上的通孔掩模，所述通孔掩模具有至少部分地与所述支柱重叠的掩模开口。 使用通孔掩模在电介质层中蚀刻通孔开口，掩模开口在第一方向上限定通孔开口的第一横向尺寸，并且柱沿不同于第一方向的第二方向限定通孔开口的第二横向尺寸 方向。 通孔开口填充有导体以形成通孔。 还提供了半导体器件和通孔结构。

公开(公告)号：US11588105B2

公开(公告)日：2023-02-21

申请号：US17198775

申请日：2021-03-11

Applicant: International Business Machines Corporation

Inventor： Praneet Adusumilli ,  Takashi Ando ,  Reinaldo Vega ,  Cheng Chi

IPC: G11C11/00 ,  H01L45/00 ,  G11C13/00

Abstract: A device includes an electronic component, and the electronic component includes a first pad, a second pad, and a strip connecting the first pad and the second pad. The device further includes a first electrode in contact with the first pad and a second electrode in contact with the second pad. The electronic component is made of a phase change material. At least one of the first electrode and the second electrode is coated with a material that is configured to increase a difference in workfunction between the first electrode and the second electrode.

公开(公告)号：US20220209018A1

公开(公告)日：2022-06-30

申请号：US17139053

申请日：2020-12-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Reinaldo Vega ,  Takashi Ando ,  Cheng Chi ,  Praneet Adusumilli

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L27/092

Abstract: A field effect transistor (FET) device is provided. The device includes an isolation region on a support substrate that separates a first back gate from a second back gate, and a gate dielectric layer on a first channel region and a second channel region. The device further includes a conductive gate layer having a work function value and a ferroelectric layer on the gate dielectric layer, wherein the first back gate can adjust a threshold voltage for the first channel region, and the second back gate can adjust a threshold voltage for the second channel region.

公开(公告)号：US20220199787A1

公开(公告)日：2022-06-23

申请号：US17132980

申请日：2020-12-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Ekmini Anuja De Silva ,  Jing Guo ,  Hao Tang ,  Cheng Chi

IPC: H01L29/417 ,  H01L29/40 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786 ,  H01L29/08

Abstract: A field effect transistor is provided. The field effect transistor includes a first source/drain on a substrate, a second source/drain on the substrate, and a channel region between the first source/drain and the second source/drain. The field effect transistor further includes a metal liner on at least three sides of the first source/drain and/or the second source/drain, wherein the metal liner covers less than the full length of a sidewall of the first source/drain and/or the second source/drain. The field effect transistor further includes a metal-silicide between the metal liner and the first source/drain and/or the second source/drain, and a conductive contact on the metal liner on the first source/drain and/or the second source/drain, wherein the conductive contact is a conductive material different from the conductive material of the metal liner.

公开(公告)号：US20220181252A1

公开(公告)日：2022-06-09

申请号：US17110381

申请日：2020-12-03

Applicant: International Business Machines Corporation

Inventor： Reinaldo Vega ,  David Wolpert ,  Takashi Ando ,  Praneet Adusumilli ,  Cheng Chi

IPC: H01L23/522 ,  H01L23/528 ,  H01L29/423 ,  H01L29/66 ,  H01L29/94 ,  H01L49/02

Abstract: An approach to forming a semiconductor device where the semiconductor device includes a first power rail with one or more vertically stacked contact vias connecting to the first power rail to a portion of a first de-coupling capacitor. The semiconductor device includes the first de-coupling capacitor in a first portion of a semiconductor substrate in a first gate cut trench.

公开(公告)号：US11205592B2

公开(公告)日：2021-12-21

申请号：US16744456

申请日：2020-01-16

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Cheng Chi ,  Chih-Chao Yang ,  Kangguo Cheng

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/285 ,  H01L23/532

Abstract: A back end of line interconnect structure and methods for forming the interconnect structure including a self-aligned via generally includes a subtractive etch process to define the vias. The vias include a via core and a liner to provide a critical dimension equal to a critical dimension of an underlying metal line. The metal lines are free of the liner. The method provides some via metal liner material on top of metal lines that do not includes a via in direct contact therewith.