公开(公告)号：US20240213337A1

公开(公告)日：2024-06-27

申请号：US18069970

申请日：2022-12-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Tsung-Sheng Kang ,  Tao Li ,  Ruilong Xie ,  Chih-Chao Yang

IPC: H01L29/417 ,  H01L23/528

CPC classification number: H01L29/41758 ,  H01L23/5286

Abstract: A semiconductor device includes at least a direct backside contact between a source line and a source epitaxial growth and/or a drain line and a drain epitaxial growth. A clock signal line contact via can connect a gate to a backside clock signal line. The clock signal line contact via is surrounded by a deep STI fill to prevent shorting between the clock signal line and the source and/or drain lines in the backside power rail.

公开(公告)号：US20240206345A1

公开(公告)日：2024-06-20

申请号：US18065651

申请日：2022-12-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ashim Dutta ,  Shravana Kumar Katakam ,  Chih-Chao Yang

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H01L43/02 ,  H01L27/222 ,  H01L43/12

Abstract: A magnetic tunnel junction (MTJ) stack, and a metallic encapsulation layer surrounding vertical side surfaces of the MTJ stack, electrically and physically connected to a top electrode of the MTJ stack. A magnetic tunnel junction (MTJ) stack, and a metallic encapsulation layer surrounding vertical side surfaces of the MTJ stack, electrically and physically connected to a top electrode of the MTJ stack, where a lower horizontal surface of the metallic encapsulation layer is below a bottom electrode contact of the MTJ stack. Forming a magnetic tunnel junction (MTJ) stack and forming a metallic encapsulation layer surrounding vertical side surfaces of the MTJ stack, electrically and physically connected to a top electrode of the MTJ stack.

公开(公告)号：US20240194691A1

公开(公告)日：2024-06-13

申请号：US18064954

申请日：2022-12-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Tao Li ,  Nicholas Alexander POLOMOFF ,  Chih-Chao Yang

IPC: H01L27/12

CPC classification number: H01L27/124 ,  H01L27/1266 ,  H01L27/1251

Abstract: A first backside power rail directly below and connected to a first source-drain epitaxy region of a positive field effect transistor (p-FET) region via a first backside contact vertically aligned with the first source-drain epitaxy region, the first backside power rail directly contacts an upper horizontal surface of the first backside contact and the first backside power rail directly contacts a vertical side surface of the first backside contact. Forming a first backside power rail directly below and connected to a first source-drain epitaxy region of a positive field effect transistor (p-FET) region via a first backside contact vertically aligned with the first source-drain epitaxy region, where the first backside power rail directly contacts an upper horizontal surface of the first backside contact and the first backside power rail directly contacts a vertical side surface of the first backside contact.

公开(公告)号：US20240188446A1

公开(公告)日：2024-06-06

申请号：US18061491

申请日：2022-12-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Shravana Kumar Katakam ,  Ashim Dutta ,  Chih-Chao Yang

IPC: H10N50/01 ,  G11C11/16 ,  H01L23/522 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80

CPC classification number: H01L43/12 ,  G11C11/161 ,  G11C11/1657 ,  H01L23/5226 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08

Abstract: A semiconductor device including a magnetic tunnel junction (MTJ) stack and an upper word line of the MTJ stack surrounding vertical side surfaces of the MTJ stack. A semiconductor device including a magnetic tunnel junction (MTJ) stack and an upper word line for the MTJ stack surrounding vertical side surfaces and an upper surface of a reference layer of the MTJ stack. A method including forming a forming a magnetic tunnel junction (MTJ) stack and forming a dielectric encapsulation layer surrounding vertical side surfaces of a top electrode, a free layer, a tunneling barrier, a reference layer and a bottom electrode of the MTJ stack.

公开(公告)号：US20240153868A1

公开(公告)日：2024-05-09

申请号：US18053772

申请日：2022-11-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Koichi Motoyama ,  Oscar van der Straten ,  Ruilong Xie ,  Chih-Chao Yang

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/53238 ,  H01L23/53266

Abstract: Embodiments of present invention provide an interconnect structure. The interconnect structure includes a first metal line in a first inter-level dielectric (ILD) layer; one or more second metal lines in a second ILD layer above the first metal line and above the first ILD layer; a third metal line in a third ILD layer above the one or more second metal lines and above the second ILD layer; and a skipvia connecting the third metal line with the first metal line, wherein the first, the one or more second, and the third metal lines are made of a first conductive material and the skipvia is made of a second conductive material, and the first conductive material is different from the second conductive material. A method of forming the above interconnect structure is also provided.

公开(公告)号：US20240130242A1

公开(公告)日：2024-04-18

申请号：US18046162

申请日：2022-10-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ailian Zhao ,  Wu-Chang Tsai ,  Ashim Dutta ,  Chih-Chao Yang

IPC: H01L43/08 ,  H01L23/48 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12

CPC classification number: H01L43/08 ,  H01L23/481 ,  H01L27/222 ,  H01L43/02 ,  H01L43/12

Abstract: Embodiments of present invention provide a method of forming a MRAM structure. The method includes forming at least one magnetic tunnel junction (MTJ) stack on top of a supporting structure; forming a conformal liner surrounding a sidewall of the MTJ stack; forming a first dielectric layer surrounding the conformal liner; selectively forming a metal oxide layer on top of the conformal liner and the first dielectric layer, the metal oxide layer having at least a first opening that exposes a top surface of the MTJ stack; and forming a top contact contacting the top surface of the MTJ stack through the first opening in the metal oxide layer. An MRAM structure formed thereby is also provided.

公开(公告)号：US20240105612A1

公开(公告)日：2024-03-28

申请号：US17954514

申请日：2022-09-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Nicholas Alexander Polomoff ,  Brent A. Anderson ,  Chih-Chao Yang

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/48 ,  H01L29/417

CPC classification number: H01L23/5286 ,  H01L21/76898 ,  H01L23/481 ,  H01L29/41725

Abstract: A semiconductor structure is presented including a device layer having a plurality of active devices, back-end-of-line (BEOL) components disposed under the device layer, a power distribution network (PDN) disposed over the device layer, and backside transistors disposed on a single crystal silicon (Si) layer disposed over the PDN. A through silicon via (TSV) extends from the backside transistors disposed on the single crystal Si layer through the BEOL. An upper TSV (uTSV) extends from the PDN through the backside transistors disposed on the single crystal Si layer to additional interconnects.

公开(公告)号：US20240096978A1

公开(公告)日：2024-03-21

申请号：US17946017

申请日：2022-09-15

Applicant: International Business Machines Corporation

Inventor： Tsung-Sheng Kang ,  Tao Li ,  Ruilong Xie ,  Chih-Chao Yang

IPC: H01L29/417 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/41733 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: A CMOS apparatus includes an n-doped field effect transistor (nFET); and a p-doped field effect transistor (pFET), each of which has a source structure and a drain structure. A common backside drain contact, which is disposed at the backside surface of the nFET and the pFET, electrically connects the nFET drain structure and the pFET drain structure to a backside interconnect layer.

公开(公告)号：US11937514B2

公开(公告)日：2024-03-19

申请号：US17313403

申请日：2021-05-06

Applicant: International Business Machines Corporation

Inventor： Theodorus E. Standaert ,  Daniel Charles Edelstein ,  Chih-Chao Yang

IPC: H10N50/01 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10B63/00 ,  H10N70/011 ,  H10N70/231 ,  H10N70/841

Abstract: A semiconductor structure forms two or more tightly pitched memory devices using a dielectric material for a gap fill material. The approach includes providing two adjacent bottom electrodes in a layer of an insulating material and above a metal layer. Two adjacent pillars are each above one of the two adjacent bottom electrodes where each pillar of the two adjacent pillars is composed of a stack of materials for a memory device. A spacer is around the vertical sides each of the two adjacent pillars. The dielectric material is on the spacer around the vertical sides each of the two adjacent pillars, on the layer of the insulating material between the two adjacent bottom electrodes. The dielectric material fills at least a first portion of a gap between the two adjacent pillars. A low k material covers the dielectric material and exposed portions of the layer of the insulating material.

公开(公告)号：US11908888B2

公开(公告)日：2024-02-20

申请号：US17482565

申请日：2021-09-23

Applicant: International Business Machines Corporation

Inventor： Baozhen Li ,  Chih-Chao Yang ,  Nan Jing ,  Huimei Zhou

IPC: H01L49/02

CPC classification number: H01L28/60

Abstract: A metal-insulator-metal (MIM) capacitor structure includes a substrate extending along a first direction to define a length, a second direction orthogonal to the first direction to define a width, and a third direction orthogonal to the first and second direction to define a height. The substrate includes a first capacitance region and a second capacitance region. The first capacitance region has a first maximum operating voltage (Vmax) and the second capacitance region has a second Vmax that is greater than the first Vmax.