利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

50 条记录 (耗时 0.021 秒)

    Bipolar junction transistors with a link region connecting the intrinsic and extrinsic bases
    15.
    发明授权
    Bipolar junction transistors with a link region connecting the intrinsic and extrinsic bases 有权
    具有连接内在和外在基极的连接区域的双极结晶体管

    公开(公告)号：US08716837B2

    公开(公告)日：2014-05-06

    申请号：US13758204

    申请日：2013-02-04

    申请人： International Business Machines Corporation

    发明人： Renata Camillo-Castillo ,  Peter B. Gray ,  David L. Harame ,  Alvin J. Joseph ,  Marwan H. Khater ,  Qizhi Liu

    IPC分类号： H01L21/02 ,  H01L21/331

    CPC分类号： H01L29/73 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0821 ,  H01L29/107 ,  H01L29/66272 ,  H01L29/7322

    摘要： Methods for fabricating bipolar junction transistors, bipolar junction transistors made by the methods, and design structures for a bipolar junction transistor. The bipolar junction transistor includes a dielectric layer on an intrinsic base and an extrinsic base at least partially separated from the intrinsic base by the dielectric layer. An emitter opening extends through the extrinsic base and the dielectric layer. The dielectric layer is recessed laterally relative to the emitter opening to define a cavity between the intrinsic base and the extrinsic base. The cavity is filled with a semiconductor layer that physically links the extrinsic base and the intrinsic base together.

    摘要翻译： 用于制造双极结型晶体管的方法，通过该方法制造的双极结型晶体管以及双极结型晶体管的设计结构。 双极结晶体管包括在本征基极上的电介质层和通过电介质层至少部分地与本征基极分离的外部基极。 发射极开口延伸穿过外部基极和电介质层。 电介质层相对于发射器开口横向凹入以限定内部基极和外部基极之间的腔。 空腔填充有将外部基极和内在基极物理连接在一起的半导体层。

    SELF-ALIGNED EMITTER-BASE BIPOLAR JUNCTION TRANSISTOR WITH REDUCED BASE RESISTANCE AND BASE-COLLECTOR CAPACITANCE
    16.
    发明申请
    SELF-ALIGNED EMITTER-BASE BIPOLAR JUNCTION TRANSISTOR WITH REDUCED BASE RESISTANCE AND BASE-COLLECTOR CAPACITANCE 有权
    具有降低基极电阻和基极集电极电容的自对准发射极基极双极晶体管

    公开(公告)号：US20160043203A1

    公开(公告)日：2016-02-11

    申请号：US14451716

    申请日：2014-08-05

    申请人： International Business Machines Corporation

    发明人： Deborah A. Alperstein ,  David L. Harame ,  Alvin J. Joseph ,  Qizhi Liu ,  Keith J. Machia ,  Christa R. Willets

    IPC分类号： H01L29/737 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

    CPC分类号： H01L29/41708 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/42304 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7371

    摘要： Device structures and fabrication methods for a bipolar junction transistor. A first semiconductor layer is formed on a substrate containing a first terminal. An etch stop layer is formed on the first semiconductor layer, and a second semiconductor layer is formed on the etch stop layer. The second semiconductor layer is etched to define a second terminal at a location of an etch mask on the second semiconductor layer. A first material comprising the etch stop layer and a second material comprising the second semiconductor layer are selected such that the second material of the second semiconductor layer etches at a greater etch rate than the first material of the etch stop layer. The first semiconductor layer may be a base layer that is used to form an intrinsic base and an extrinsic base of the bipolar junction transistor.

    摘要翻译： 双极结型晶体管的器件结构和制造方法。 在包含第一端子的基板上形成第一半导体层。 在第一半导体层上形成蚀刻停止层，在蚀刻停止层上形成第二半导体层。 蚀刻第二半导体层以在第二半导体层上的蚀刻掩模的位置处限定第二端子。 选择包括蚀刻停止层的第一材料和包括第二半导体层的第二材料，使得第二半导体层的第二材料以比蚀刻停止层的第一材料更高的蚀刻速率蚀刻。 第一半导体层可以是用于形成双极结型晶体管的本征基极和非本征基极的基极层。

    Semiconductor fins on a trench isolation region in a bulk semiconductor substrate and a method of forming the semiconductor fins
    17.
    发明授权
    Semiconductor fins on a trench isolation region in a bulk semiconductor substrate and a method of forming the semiconductor fins 有权
    体半导体衬底中的沟槽隔离区域上的半导体鳍片和形成半导体鳍片的方法

    公开(公告)号：US09224841B2

    公开(公告)日：2015-12-29

    申请号：US14162403

    申请日：2014-01-23

    申请人： International Business Machines Corporation

    发明人： David L. Harame ,  Qizhi Liu ,  Edward J. Nowak

    IPC分类号： H01L31/111 ,  H01L29/66 ,  H01L21/762 ,  H01L27/088 ,  H01L21/8234

    CPC分类号： H01L29/66795 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/785

    摘要： Disclosed are semiconductor structures with monocrystalline semiconductor fins, which are above a trench isolation region in a semiconductor substrate and which can be incorporated into semiconductor device(s). Also disclosed are methods of forming such structures by forming sidewall spacers on opposing sides of mandrels on a dielectric cap layer. Between adjacent mandrels, an opening is formed that extends vertically through the dielectric cap layer and through multiple monocrystalline semiconductor layers into a semiconductor substrate. A portion of the opening within the substrate is expanded to form a trench. This trench undercuts the semiconductor layers and extends laterally below adjacent sidewall spacers on either side of the opening. The trench is then filled with an isolation layer, thereby forming a trench isolation region, and a sidewall image transfer process is performed using the sidewall spacers to form a pair of monocrystalline semiconductor fins above the trench isolation region.

    摘要翻译： 公开了具有单晶半导体鳍片的半导体结构，其在半导体衬底中的沟槽隔离区域上方并且可以并入半导体器件中。 还公开了通过在电介质盖层上的心轴的相对侧上形成侧壁间隔来形成这种结构的方法。 在相邻的心轴之间形成开口，其垂直延伸穿过电介质盖层并通过多个单晶半导体层进入半导体衬底。 衬底内的开口的一部分被扩展以形成沟槽。 该沟槽底切半导体层，并且在开口两侧的相邻侧壁间隔物侧向延伸。 然后用隔离层填充沟槽，从而形成沟槽隔离区域，并且使用侧壁间隔物进行侧壁图像转印处理，以在沟槽隔离区域上方形成一对单晶半导体鳍片。

    Integrated semiconductor devices with single crystalline beam, methods of manufacture and design structure
    18.
    发明授权
    Integrated semiconductor devices with single crystalline beam, methods of manufacture and design structure 有权
    具有单晶束的集成半导体器件，制造方法和设计结构

    公开(公告)号：US09172025B2

    公开(公告)日：2015-10-27

    申请号：US14713327

    申请日：2015-05-15

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： David L. Harame ,  Stephen E. Luce ,  Anthony K. Stamper

    IPC分类号： H01L21/70 ,  H01L21/76 ,  H01L41/083 ,  H01L41/08

    CPC分类号： H01L41/083 ,  G06F17/5068 ,  H01L21/84 ,  H01L27/1203 ,  H01L41/081 ,  H01L41/094 ,  H01L41/332 ,  H03H3/02 ,  H03H9/1007 ,  H03H9/173 ,  H03H2001/0064 ,  H03H2003/027 ,  H03H2009/155

    摘要： Bulk acoustic wave filters and/or bulk acoustic resonators integrated with CMOS devices, are provided. The structure includes a single crystalline beam formed from a silicon layer of a silicon on insulator (SOI) substrate; insulator material coating the single crystalline beam; an upper cavity formed above the single crystalline beam, over a portion of the insulator material; a lower cavity formed in lower wafer bonded to an insulator layer of the SOI substrate, below the single crystalline beam and the insulator layer of the SOI substrate; a connecting via that connects the upper cavity to the lower cavity, the connecting via being coated with the insulator material; and a Bulk Acoustic Wave (BAW) filter or Bulk Acoustic Resonator (BAR) in electrical connection with the single crystalline beam.

    摘要翻译： 提供了与CMOS器件集成的体声波滤波器和/或体声波谐振器。 该结构包括由绝缘体上硅（SOI）衬底的硅层形成的单晶束; 绝缘体材料涂覆单晶束; 形成在单晶束上方的上腔，超过绝缘体材料的一部分; 在下晶片上形成的下腔体，其结合到SOI衬底的绝缘体层，在单晶束和SOI衬底的绝缘体层之下; 连接通孔，其将上腔体连接到下腔体，连接通孔被绝缘体材料涂覆; 以及与单晶束电连接的体声波（BAW）滤波器或体声声谐振器（BAR）。

    Integrated semiconductor devices with single crystalline beam, methods of manufacture and design structure
    19.
    发明授权
    Integrated semiconductor devices with single crystalline beam, methods of manufacture and design structure 有权
    具有单晶束的集成半导体器件，制造方法和设计结构

    公开(公告)号：US09059396B2

    公开(公告)日：2015-06-16

    申请号：US14024171

    申请日：2013-09-11

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： David L. Harame ,  Stephen E. Luce ,  Anthony K. Stamper

    IPC分类号： H01L21/76 ,  H01L21/70 ,  H01L41/09 ,  G06F17/50 ,  H01L21/84 ,  H01L27/12 ,  H03H3/02 ,  H03H9/10 ,  H03H9/17 ,  H01L41/332 ,  H03H1/00 ,  H03H9/15

    CPC分类号： H01L41/083 ,  G06F17/5068 ,  H01L21/84 ,  H01L27/1203 ,  H01L41/081 ,  H01L41/094 ,  H01L41/332 ,  H03H3/02 ,  H03H9/1007 ,  H03H9/173 ,  H03H2001/0064 ,  H03H2003/027 ,  H03H2009/155

    摘要： Bulk acoustic wave filters and/or bulk acoustic resonators integrated with CMOS devices, methods of manufacture and design structure are provided. The method includes forming a single crystalline beam from a silicon layer on an insulator. The method further includes providing a coating of insulator material over the single crystalline beam. The method further includes forming a via through the insulator material. The method further includes providing a sacrificial material in the via and over the insulator material. The method further includes providing a lid on the sacrificial material. The method further includes providing further sacrificial material in a trench of a lower wafer. The method further includes bonding the lower wafer to the insulator, under the single crystalline beam. The method further includes venting the sacrificial material and the further sacrificial material to form an upper cavity above the single crystalline beam and a lower cavity, below the single crystalline beam.

    摘要翻译： 提供了与CMOS器件集成的体声波滤波器和/或体声波谐振器，制造方法和设计结构。 该方法包括从绝缘体上的硅层形成单晶束。 该方法还包括在单晶束上提供绝缘体材料涂层。 该方法还包括通过绝缘体材料形成通孔。 该方法还包括在通孔和绝缘体材料上提供牺牲材料。 该方法还包括在牺牲材料上提供盖子。 该方法还包括在下晶片的沟槽中提供另外的牺牲材料。 该方法还包括在单晶束下将下晶片接合到绝缘体。 该方法还包括排出牺牲材料和另外的牺牲材料，以在单晶束之下形成单结晶束上方的上空腔和在单晶束下方的下腔。