公开(公告)号：US11700778B2

公开(公告)日：2023-07-11

申请号：US17226495

申请日：2021-04-09

Applicant: TOKYO ELECTRON LIMITED ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Steven Consiglio ,  Cory Wajda ,  Kandabara Tapily ,  Takaaki Tsunomura ,  Takashi Ando ,  Paul C. Jamison ,  Eduard A. Cartier ,  Vijay Narayanan ,  Marinus J. P. Hopstaken

IPC: H01L45/00 ,  H10N70/00 ,  H10B63/00

CPC classification number: H10N70/023 ,  H10B63/00 ,  H10N70/8833

Abstract: A method of controlling the forming voltage of a dielectric film in a resistive random access memory (ReRAM) device. The method includes depositing a dielectric film contains intrinsic defects on a substrate, forming a plasma-excited treatment gas containing H2 gas, and exposing the dielectric film to the plasma-excited treatment gas to create additional defects in the dielectric film without substantially changing a physical thickness of the dielectric film, where the additional defects lower the forming voltage needed for generating an electrically conducting filament across the dielectric film. The dielectric film can include a metal oxide film and the plasma-excited treatment gas may be formed using a microwave plasma source.

公开(公告)号：US10991881B2

公开(公告)日：2021-04-27

申请号：US16428554

申请日：2019-05-31

Applicant: TOKYO ELECTRON LIMITED ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Steven Consiglio ,  Cory Wajda ,  Kandabara Tapily ,  Takaaki Tsunomura ,  Takashi Ando ,  Paul C. Jamison ,  Eduard A. Cartier ,  Vijay Narayanan ,  Marinus J. P. Hopstaken

IPC: H01L45/00 ,  H01L27/24

Abstract: A method of controlling the forming voltage of a dielectric film in a resistive random access memory (ReRAM) device. The method includes depositing a dielectric film contains intrinsic defects on a substrate, forming a plasma-excited treatment gas containing H2 gas, and exposing the dielectric film to the plasma-excited treatment gas to create additional defects in the dielectric film without substantially changing a physical thickness of the dielectric film, where the additional defects lower the forming voltage needed for generating an electrically conducting filament across the dielectric film. The dielectric film can include a metal oxide film and the plasma-excited treatment gas may be formed using a microwave plasma source.

公开(公告)号：US10886362B2

公开(公告)日：2021-01-05

申请号：US15706047

申请日：2017-09-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Hemanth Jagannathan ,  Paul C. Jamison

IPC: H01L21/60 ,  H01L49/02 ,  H01L21/02

Abstract: A tri-layer dielectric stack is provided for a metal-insulator-metal capacitor (MIMCAP). Also, a metal-insulator-metal capacitor (MIMCAP) is provided having three or more electrodes. The tri-layer dielectric stack includes a first layer formed from a first metal oxide electrical insulator. The tri-layer dielectric stack further includes a second layer, disposed over the first layer, formed from ZrO2. The tri-layer dielectric stack also includes a third layer, disposed over the second layer, formed from a second metal oxide electrical insulator.

公开(公告)号：US20200019731A1

公开(公告)日：2020-01-16

申请号：US16578319

申请日：2019-09-21

Applicant: International Business Machines Corporation

Inventor： Richard H. Boivie ,  Eduard A. Cartier ,  Daniel J. Friedman ,  Kohji Hosokawa ,  Charanjit Jutla ,  Wanki Kim ,  Chandrasekara Kothandaraman ,  Chung Lam ,  Frank R. Libsch ,  Seiji Munetoh ,  Ramachandran Muralidhar ,  Vijay Narayanan ,  Dirk Pfeiffer ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Robert L. Wisnieff

IPC: G06F21/72 ,  G11C16/00 ,  G06F21/75

Abstract: A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.

公开(公告)号：US20190273205A1

公开(公告)日：2019-09-05

申请号：US15911821

申请日：2018-03-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Seyoung Kim ,  John Bruley

IPC: H01L45/00

Abstract: A method is presented for increasing resistance of a resistive random access memory (ReRAM) device. The method includes forming a first electrode, forming an insulating layer over the first electrode, and forming a second electrode over the insulating layer, the second electrode constructed by depositing a stoichiometric oxygen barrier layer and depositing an oxidized conducting layer directly over the stoichiometric oxygen barrier layer to create a high-resistance conductive path between the first and second electrodes of the ReRAM device.

公开(公告)号：US10361093B2

公开(公告)日：2019-07-23

申请号：US15647590

申请日：2017-07-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Chandrasekharan Kothandaraman

IPC: H01L27/11521 ,  H01L29/788 ,  H01L21/3115 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8234 ,  H01L21/28 ,  H01L29/66 ,  H01L29/792 ,  G11C16/04 ,  H01L27/11568

Abstract: A metal oxide semiconductor field effect transistors (MOSFET) memory array, including a complementary metal oxide semiconductor (CMOS) cell including an n-type MOSFET having a modified gate dielectric; and an n-type or p-type MOSFET having an unmodified gate dielectric layer, where the modified gate dielectric layer incorporates an oxygen scavenging species.

公开(公告)号：US20180277621A1

公开(公告)日：2018-09-27

申请号：US15832250

申请日：2017-12-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Hemanth Jagannathan ,  Paul C. Jamison ,  Vijay Narayanan

IPC: H01L49/02 ,  H01L21/285 ,  H01L21/02

CPC classification number: H01L28/91 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/0228 ,  H01L21/28568 ,  H01L23/481 ,  H01L23/5223 ,  H01L28/40 ,  H01L28/60 ,  H01L28/75 ,  H01L28/90

Abstract: A method for forming a metal-insulator-metal (MIM) capacitor on a semiconductor substrate is presented. The method includes forming a first electrode defining columnar grains, forming a dielectric layer over the first electrode, and forming a second electrode over the dielectric layer. The first and second electrodes can be titanium nitride (TiN) electrodes. The dielectric layer can include one of hafnium oxide and zirconium oxide deposited by atomic layer deposition (ALD). The ALD results in deposition of high-k films in grain boundaries of the first electrode.

公开(公告)号：US20180240863A1

公开(公告)日：2018-08-23

申请号：US15706126

申请日：2017-09-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Hemanth Jagannathan ,  Paul C. Jamison

IPC: H01L49/02 ,  H01L21/02 ,  H01L21/3205

CPC classification number: H01L28/60 ,  H01L21/02178 ,  H01L21/02189 ,  H01L21/32051

Abstract: A tri-layer dielectric stack is provided for a metal-insulator-metal capacitor (MIMCAP). Also, a metal-insulator-metal capacitor (MIMCAP) is provided having three or more electrodes. The tri-layer dielectric stack includes a first layer formed from a first metal oxide electrical insulator. The tri-layer dielectric stack further includes a second layer, disposed over the first layer, formed from ZrO2. The tri-layer dielectric stack also includes a third layer, disposed over the second layer, formed from a second metal oxide electrical insulator.

公开(公告)号：US09972697B2

公开(公告)日：2018-05-15

申请号：US15267887

申请日：2016-09-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Kisik Choi ,  Vijay Narayanan

IPC: H01L21/3205 ,  H01L29/66 ,  H01L21/28 ,  H01L21/324 ,  H01L29/423 ,  H01L21/321 ,  H01L21/02

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/28017 ,  H01L21/28088 ,  H01L21/32055 ,  H01L21/321 ,  H01L21/324 ,  H01L29/4232 ,  H01L29/66 ,  H01L29/66795 ,  H01L29/6681

Abstract: A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.

公开(公告)号：US20170309487A1

公开(公告)日：2017-10-26

申请号：US15133656

申请日：2016-04-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  John Bruley ,  Eduard A. Cartier ,  Martin M. Frank ,  Vijay Narayanan ,  John Rozen

IPC: H01L21/28 ,  H01L29/40 ,  H01L29/51

CPC classification number: H01L21/28255 ,  H01L21/28229 ,  H01L21/28264 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

Abstract: A method of forming a semiconductor device that includes forming a metal oxide material on a III-V semiconductor channel region or a germanium containing channel region; and treating the metal oxide material with an oxidation process. The method may further include depositing of a hafnium containing oxide on the metal oxide material after the oxidation process, and forming a gate conductor atop the hafnium containing oxide. The source and drain regions are on present on opposing sides of the gate structure including the metal oxide material, the hafnium containing oxide and the gate conductor.