公开(公告)号：US11152265B2

公开(公告)日：2021-10-19

申请号：US16528748

申请日：2019-08-01

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Hemanth Jagannathan ,  Christopher J. Waskiewicz ,  Alexander Reznicek

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L21/762 ,  H01L29/78

Abstract: A vertical field effect transistor structure and method for fabricating the same. The structure includes a source/drain layer in contact with at least one semiconductor fin. An edge portion of the source/drain layer includes a notched region filled with a dielectric material. A spacer layer includes a first portion in contact with the source/drain layer and a second portion in contact with the dielectric material. A gate structure contacts the spacer layer and the dielectric material. The method includes forming a source/drain layer in contact with at least one semiconductor fin. A spacer layer is formed in contact with the source/drain layer. A portion of the spacer layer is removed to expose an end portion of the source/drain layer. The exposed end portion of the source/drain layer is recessed to form a notched region within the source/drain layer. A dielectric layer is formed within the notched region.

公开(公告)号：US11088033B2

公开(公告)日：2021-08-10

申请号：US15259626

申请日：2016-09-08

Applicant: International Business Machines Corporation

Inventor： Praneet Adusumilli ,  Hemanth Jagannathan ,  Christian Lavoie ,  Ahmet S. Ozcan

IPC: H01L29/15 ,  H01L21/8238 ,  H01L29/06 ,  H01L21/3215 ,  H01L21/265 ,  H01L21/285 ,  H01L29/45 ,  H01L29/66 ,  H01L27/092 ,  H01L21/84 ,  H01L27/12 ,  H01L29/16 ,  H01L29/161 ,  H01L29/24 ,  H01L29/423 ,  H01L29/786 ,  H01L21/768

Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least one semiconductor fin disposed on a substrate. A disposable gate contacts the at least one semiconductor fin. A spacer is disposed on the at least one semiconductor fin and in contact with the disposable gate. Epitaxially grown source and drain regions are disposed at least partially within the at least one semiconductor fin. A first one of silicide and germanide is disposed on and in contact with the source region. A second one of one of silicide and germanide is disposed on and in contact with the drain region. The method includes epitaxially growing source/drain regions within a semiconductor fin. A contact metal layer contacts the source/drain regions. One of a silicide and a germanide is formed on the source/drain regions from the contact metal layer prior to removing the disposable gate.

公开(公告)号：US10971626B2

公开(公告)日：2021-04-06

申请号：US16502685

申请日：2019-07-03

Applicant: International Business Machines Corporation

Inventor： Devendra Sadana ,  Dechao Guo ,  Joel P. de Souza ,  Ruqiang Bao ,  Stephen W. Bedell ,  Shogo Mochizuki ,  Gen Tsutsui ,  Hemanth Jagannathan ,  Marinus Hopstaken

IPC: H01L29/66 ,  H01L21/762 ,  H01L29/78 ,  H01L21/02 ,  H01L29/161 ,  H01L29/04 ,  H01L29/10 ,  H01L29/423 ,  H01L29/786 ,  H01L29/51

Abstract: Techniques for interface charge reduction to improve performance of SiGe channel devices are provided. In one aspect, a method for reducing interface charge density (Dit) for a SiGe channel material includes: contacting the SiGe channel material with an Si-containing chemical precursor under conditions sufficient to form a thin continuous Si layer, e.g., less than 5 monolayers thick on a surface of the SiGe channel material which is optionally contacted with an n-dopant precursor; and depositing a gate dielectric on the SiGe channel material over the thin continuous Si layer, wherein the thin continuous Si layer by itself or in conjunction with n-dopant precursor passivates an interface between the SiGe channel material and the gate dielectric thereby reducing the Dit. A FET device and method for formation thereof are also provided.

公开(公告)号：US10937890B2

公开(公告)日：2021-03-02

申请号：US16373844

申请日：2019-04-03

Applicant: International Business Machines Corporation

Inventor： Wenyu Xu ,  Ruilong Xie ,  Pietro Montanini ,  Hemanth Jagannathan

IPC: H01L21/82 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/311 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/45 ,  H01L29/49

Abstract: A method for forming a semiconductor device is disclosed. The method includes receiving a substrate stack including at least one semiconductor fin, the substrate stack including: a bottom source/drain epi region directly below the semiconductor fin; a vertical gate structure directly above the bottom source/drain epi region and in contact with the semiconductor fin; a first inter-layer dielectric in contact with a sidewall of the vertical gate structure; and a second interlayer-layer dielectric directly above and contacting a top surface of the first inter-layer dielectric. The method further including: etching a top region of the semiconductor fin and the gate structure thereby creating a recess directly above the top region of the semiconductor fin and the vertical gate structure; and forming in the recess a top source/drain epi region directly above, and contacting, a top surface of the semiconductor fin. A novel semiconductor device structure is also disclosed.

公开(公告)号：US10833173B2

公开(公告)日：2020-11-10

申请号：US16117106

申请日：2018-08-30

Applicant: International Business Machines Corporation

Inventor： Christopher J. Waskiewicz ,  Su Chen Fan ,  Hari Prasad Amanapu ,  Hemanth Jagannathan

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/08 ,  H01L21/768 ,  H01L29/78

Abstract: A semiconductor includes a semiconductor substrate having a bottom source/drain region and a vertical semiconductor fin having a bottom end that contacts the semiconductor substrate. The semiconductor device further includes a top source/drain region on a top end of the vertical semiconductor. The top source/drain region is separated from the semiconductor substrate by the vertical semiconductor fin. The semiconductor device further includes an electrically conductive cap on an outer surface of the top source/drain region.

公开(公告)号：US10833150B2

公开(公告)日：2020-11-10

申请号：US16032632

申请日：2018-07-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Martin M. Frank ,  Kam-Leung Lee ,  Eduard A. Cartier ,  Vijay Narayanan ,  Jean Fompeyrine ,  Stefan Abel ,  Oleg Gluschenkov ,  Hemanth Jagannathan

IPC: H01L21/00 ,  H01L29/04 ,  H01L21/02 ,  H01L29/06 ,  H01L29/51

Abstract: A method for converting a dielectric material including a type IV transition metal into a crystalline material that includes forming a predominantly non-crystalline dielectric material including the type IV transition metal on a supporting substrate as a component of an electrical device having a scale of microscale or less; and converting the predominantly non-crystalline dielectric material including the type IV transition metal to a crystalline crystal structure by exposure to energy for durations of less than 100 milliseconds and, in some instances, less than 10 microseconds. The resultant material is fully or partially crystallized and contains a metastable ferroelectric phase such as the polar orthorhombic phase of space group Pca21 or Pmn21. During the conversion to the crystalline crystal structure, adjacently positioned components of the electrical devices are not damaged.

公开(公告)号：US10714399B2

公开(公告)日：2020-07-14

申请号：US16106412

申请日：2018-08-21

Applicant: International Business Machines Corporation

Inventor： Shogo Mochizuki ,  ChoongHyun Lee ,  Hemanth Jagannathan

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/02 ,  H01L21/265 ,  H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L29/08 ,  H01L29/49 ,  H01L21/324

Abstract: A method of forming a semiconductor structure includes forming a plurality of fins over a top surface of a substrate, and forming one or more vertical transport field-effect transistors from the plurality of fins, the plurality of fins providing channels for the one or more vertical transport field-effect transistors. The method also includes forming a gate stack for the one or more vertical transport field-effect transistors surrounding at least a portion of the plurality of fins, the gate stack including a gate dielectric formed over the plurality of fins, a work function metal layer formed over the gate dielectric, and a gate conductor formed over the work function metal layer. The gate stack comprises a box profile in an area between at least two adjacent ones of the plurality of fins.

公开(公告)号：US20200185381A1

公开(公告)日：2020-06-11

申请号：US16788229

申请日：2020-02-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Ruqiang Bao ,  Hemanth Jagannathan ,  ChoongHyun Lee

IPC: H01L27/088 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/098

Abstract: A method of fabricating a plurality of field effect transistors with different threshold voltages, including forming a cover layer on a channel region in a first subset, forming a first sacrificial layer on two or more channel regions in a second subset, forming a second sacrificial layer on one of the two or more channel regions in the second subset, removing the cover layer from the channel region in the first subset, forming a first dummy dielectric layer on the channel region in the first subset, and forming a second dummy dielectric layer on the first dummy dielectric layer and the first sacrificial layer on the channel region in the second subset.

公开(公告)号：US20200066604A1

公开(公告)日：2020-02-27

申请号：US16106412

申请日：2018-08-21

Applicant: International Business Machines Corporation

Inventor： Shogo Mochizuki ,  ChoongHyun Lee ,  Hemanth Jagannathan

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/02 ,  H01L21/265 ,  H01L21/324 ,  H01L29/66 ,  H01L27/092 ,  H01L29/08 ,  H01L29/49 ,  H01L29/78

Abstract: A method of forming a semiconductor structure includes forming a plurality of fins over a top surface of a substrate, and forming one or more vertical transport field-effect transistors from the plurality of fins, the plurality of fins providing channels for the one or more vertical transport field-effect transistors. The method also includes forming a gate stack for the one or more vertical transport field-effect transistors surrounding at least a portion of the plurality of fins, the gate stack including a gate dielectric formed over the plurality of fins, a work function metal layer formed over the gate dielectric, and a gate conductor formed over the work function metal layer. The gate stack comprises a box profile in an area between at least two adjacent ones of the plurality of fins.

公开(公告)号：US10573565B2

公开(公告)日：2020-02-25

申请号：US16273779

申请日：2019-02-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Lisa F. Edge ,  Hemanth Jagannathan ,  Paul C. Jamison ,  Vamsi K. Paruchuri

IPC: H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L29/51 ,  H01L29/78 ,  H01L21/84 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

Abstract: An electrical device that includes a p-type semiconductor device having a p-type work function gate structure including a first high-k gate dielectric, a first metal containing buffer layer, a first titanium nitride layer having a first thickness present on the metal containing buffer layer, and a first gate conductor contact. A mid gap semiconductor device having a mid gap gate structure including a second high-k gate dielectric, a second metal containing buffer layer, a second titanium nitride layer having a second thickness that is less than the first thickness present, and a second gate conductor contact. An n-type semiconductor device having an n-type work function gate structure including a third high-k gate dielectric present on a channel region of the n-type semiconductor device, a third metal containing buffer layer on the third high-k gate dielectric and a third gate conductor fill present atop the third metal containing buffer layer.