公开(公告)号：US09818688B2

公开(公告)日：2017-11-14

申请号：US14945854

申请日：2015-11-19

Applicant: International Business Machines Corporation

Inventor： James S. Dunn ,  Zhong-Xiang He ,  Qizhi Liu

IPC: H01L23/522 ,  H01L23/66 ,  H01L49/02 ,  H01L29/06 ,  H01L21/762 ,  H01L23/31 ,  H01L23/528 ,  H01L23/532 ,  H01L29/16

CPC classification number: H01L23/5223 ,  H01L21/3083 ,  H01L21/762 ,  H01L21/76224 ,  H01L23/3171 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/53295 ,  H01L23/66 ,  H01L28/10 ,  H01L28/40 ,  H01L29/0649 ,  H01L29/16 ,  H01L2223/6672 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Structures and methods of making a dielectric region in a bulk silicon (Si) substrate of a mixed-signal integrated circuit (IC) provide a high-Q passive resonator. Deep trenches within the bulk Si substrate in directions are expanded by wet etching to form contiguous cavities, which are filled by Si oxide to form a dielectric region. The dielectric region enhances the quality (Q) of an overlying passive resonator, formed in metallization layers of the mixed-signal IC.

公开(公告)号：US09646993B2

公开(公告)日：2017-05-09

申请号：US14834696

申请日：2015-08-25

Applicant: International Business Machines Corporation

Inventor： Peng Cheng ,  James S. Dunn ,  Blaine J. Gross ,  Qizhi Liu ,  James A. Slinkman

IPC: H01L21/70 ,  H01L27/12 ,  H01L29/66 ,  H01L29/78 ,  H01L27/02 ,  H01L29/06 ,  H01L29/165 ,  H01L29/45 ,  H01L21/308 ,  H01L27/088

CPC classification number: H01L27/1203 ,  H01L21/3081 ,  H01L21/764 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/78 ,  H01L29/7842

Abstract: Various embodiments include field effect transistors (FETs) and related integrated circuit (IC) layouts. One FET includes: a silicon substrate including a set of trenches; a first oxide abutting the silicon substrate; a silicon germanium (SiGe) layer overlying the silicon substrate; a silicon layer overlying the SiGe layer; a second oxide overlying the silicon layer, wherein the silicon layer includes a plurality of salicide regions; a gate structure overlying the second oxide between adjacent salicide regions; and a first contact contacting the gate structure; a second contact contacting one of the salicide regions; a third oxide partially filling the set of trenches and extending above the silicon layer overlying the SiGe layer; and an air gap in each of the set of trenches, the air gap surrounded by the third oxide.

公开(公告)号：US20160071796A1

公开(公告)日：2016-03-10

申请号：US14945854

申请日：2015-11-19

Applicant: International Business Machines Corporation

Inventor： James S. Dunn ,  Zhong-Xiang He ,  Qizhi Liu

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/31 ,  H01L29/16 ,  H01L23/528

CPC classification number: H01L23/5223 ,  H01L21/3083 ,  H01L21/762 ,  H01L21/76224 ,  H01L23/3171 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/53295 ,  H01L23/66 ,  H01L28/10 ,  H01L28/40 ,  H01L29/0649 ,  H01L29/16 ,  H01L2223/6672 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Structures and methods of making a dielectric region in a bulk silicon (Si) substrate of a mixed-signal integrated circuit (IC) provide a high-Q passive resonator. Deep trenches within the bulk Si substrate in directions are expanded by wet etching to form contiguous cavities, which are filled by Si oxide to form a dielectric region. The dielectric region enhances the quality (Q) of an overlying passive resonator, formed in metallization layers of the mixed-signal IC.

公开(公告)号：US20150206961A1

公开(公告)日：2015-07-23

申请号：US14160630

申请日：2014-01-22

Applicant: International Business Machines Corporation

Inventor： James W. Adkisson ,  James S. Dunn ,  Blaine J. Gross ,  David L. Harame ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/423 ,  H01L29/16 ,  H01L21/28 ,  H01L29/165 ,  H01L29/15 ,  H01L29/06 ,  H01L21/02 ,  G06F17/50 ,  H01L29/161

CPC classification number: H01L29/808 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5072 ,  H01L21/28026 ,  H01L21/306 ,  H01L21/8232 ,  H01L29/0657 ,  H01L29/161 ,  H01L29/47 ,  H01L29/475 ,  H01L29/66901 ,  H01L29/66924 ,  H01L29/7782 ,  H01L29/8124

Abstract: At least one isolation trench formed in a layer stack including substrate, channel, and upper gate layers define a channel in the channel layer. Lateral etching from the isolation trench(es) can form lateral cavities in the substrate and upper gate layer to substantially simultaneously form self-aligned lower and upper gates. The lower gate undercuts the channel, the upper gate is narrower than the channel, and a source and a drain can be formed on opposed ends of the channel. As a result, source-drain capacitance and gate-drain capacitance can be reduced, increasing speed of the resulting FET.

Abstract translation: 在包括衬底，沟道和上栅极层的层堆叠中形成的至少一个隔离沟槽限定沟道层中的沟道。 来自隔离沟槽的横向蚀刻可以在衬底和上部栅极层中形成侧向空腔，以基本上同时形成自对准的下部栅极和上部栅极。 下栅极切口通道，上栅极比通道窄，并且可以在通道的相对端形成源极和漏极。 因此，可以减小源极 - 漏极电容和栅极 - 漏极电容，从而提高所产生的FET的速度。

公开(公告)号：US20150048478A1

公开(公告)日：2015-02-19

申请号：US14496430

申请日：2014-09-25

Applicant: International Business Machines Corporation

Inventor： James S. Dunn ,  Qizhi Liu

IPC: H01L29/732 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/732 ,  G06F17/5045 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/7378

Abstract: Device structures and design structures for a bipolar junction transistor. A first isolation structure is formed in a substrate to define a boundary for a device region. A collector is formed in the device region, and a second isolation structure is formed in the device region. The second isolation structure defines a boundary for the collector. The second isolation structure is laterally positioned relative to the first isolation structure to define a section of the device region between the first and second isolation structures.

Abstract translation: 双极结型晶体管的器件结构和设计结构。 第一隔离结构形成在衬底中以限定器件区域的边界。 在器件区域中形成集电极，在器件区域形成第二隔离结构。 第二个隔离结构定义了收集器的边界。 第二隔离结构相对于第一隔离结构横向定位，以限定第一和第二隔离结构之间的器件区域的一部分。

公开(公告)号：US08956945B2

公开(公告)日：2015-02-17

申请号：US13757961

申请日：2013-02-04

Applicant: International Business Machines Corporation

Inventor： James S. Dunn ,  Qizhi Liu

IPC: H01L21/331 ,  G06F17/50 ,  H01L29/66 ,  H01L29/737 ,  H01L29/06

CPC classification number: H01L29/732 ,  G06F17/5045 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/7378

Abstract: Device structures, fabrication methods, and design structures for a bipolar junction transistor. A first isolation structure is formed in a substrate to define a boundary for a device region. A collector is formed in the device region, and a second isolation structure is formed in the device region. The second isolation structure defines a boundary for the collector. The second isolation structure is laterally positioned relative to the first isolation structure to define a section of the device region between the first and second isolation structures.

Abstract translation: 双极结型晶体管的器件结构，制造方法和设计结构。 在衬底中形成第一隔离结构以限定器件区域的边界。 在器件区域中形成集电极，在器件区域形成第二隔离结构。 第二个隔离结构定义了收集器的边界。 第二隔离结构相对于第一隔离结构横向定位，以限定第一和第二隔离结构之间的器件区域的一部分。

公开(公告)号：US20140217551A1

公开(公告)日：2014-08-07

申请号：US13757961

申请日：2013-02-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： James S. Dunn ,  Qizhi Liu

IPC: H01L29/73 ,  G06F17/50 ,  H01L29/66

CPC classification number: H01L29/732 ,  G06F17/5045 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/7378

Abstract: Device structures, fabrication methods, and design structures for a bipolar junction transistor. A first isolation structure is formed in a substrate to define a boundary for a device region. A collector is formed in the device region, and a second isolation structure is formed in the device region. The second isolation structure defines a boundary for the collector. The second isolation structure is laterally positioned relative to the first isolation structure to define a section of the device region between the first and second isolation structures.

Abstract translation: 双极结型晶体管的器件结构，制造方法和设计结构。 在衬底中形成第一隔离结构以限定器件区域的边界。 在器件区域中形成集电极，在器件区域形成第二隔离结构。 第二个隔离结构定义了收集器的边界。 第二隔离结构相对于第一隔离结构横向定位，以限定第一和第二隔离结构之间的器件区域的一部分。

公开(公告)号：US20140213036A1

公开(公告)日：2014-07-31

申请号：US14230206

申请日：2014-03-31

Applicant: International Business Machines Corporation

Inventor： Alan B. Botula ,  Renata Camillo-Castillo ,  James S. Dunn ,  Jeffrey P. Gambino ,  Douglas B. Hershberger ,  Alvin J. Joseph ,  Robert M. Rassel ,  Mark E. Stidham

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/26506 ,  H01L21/823892 ,  H01L27/04 ,  H01L27/0623 ,  H01L27/0635 ,  H01L27/0802 ,  H01L27/0811 ,  H01L27/0928

Abstract: A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a bipolar transistor device and triple well, a third region having a third resistivity, with a high resistivity for a passive device, a fourth region, substantially without implantation, to provide low perimeter capacitance for devices.

Abstract translation: 衬底包括具有第一电阻率的第一区域，用于优化场效应晶体管，具有第二电阻率的第二区域，用于优化双极晶体管器件和三阱的npn子集电极，具有第三电阻率的第三区域，具有第三电阻率 用于无源器件的高电阻率，第四区域，基本上没有植入，以为器件提供低周边电容。

公开(公告)号：US09437539B2

公开(公告)日：2016-09-06

申请号：US14830816

申请日：2015-08-20

Applicant: International Business Machines Corporation

Inventor： James S. Dunn ,  Zhong-Xiang He ,  Qizhi Liu

IPC: H01L23/522 ,  H01L23/66 ,  H01L49/02 ,  H01L29/06 ,  H01L21/762 ,  H01L23/31 ,  H01L23/528 ,  H01L23/532 ,  H01L29/16

CPC classification number: H01L23/5223 ,  H01L21/3083 ,  H01L21/762 ,  H01L21/76224 ,  H01L23/3171 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/53295 ,  H01L23/66 ,  H01L28/10 ,  H01L28/40 ,  H01L29/0649 ,  H01L29/16 ,  H01L2223/6672 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Structures and methods of making a dielectric region in a bulk silicon (Si) substrate of a mixed-signal integrated circuit (IC) provide a high-Q passive resonator. Deep trenches within the bulk Si substrate in directions are expanded by wet etching to form contiguous cavities, which are filled by Si oxide to form a dielectric region. The dielectric region enhances the quality (Q) of an overlying passive resonator, formed in metallization layers of the mixed-signal IC.

Abstract translation: 在混合信号集成电路（IC）的体硅（Si）衬底中制造电介质区域的结构和方法提供了高Q无源谐振器。 通过湿法蚀刻在<100>方向内的本体Si衬底内的深沟槽扩大以形成连续的空腔，其由Si氧化物填充以形成电介质区域。 电介质区域增强了在混合信号IC的金属化层中形成的覆盖无源谐振器的质量（Q）。

公开(公告)号：US09257324B2

公开(公告)日：2016-02-09

申请号：US14230206

申请日：2014-03-31

Applicant: International Business Machines Corporation

Inventor： Alan B. Botula ,  Renata Camillo-Castillo ,  James S. Dunn ,  Jeffrey P. Gambino ,  Douglas B. Hershberger ,  Alvin J. Joseph ,  Robert M. Rassel ,  Mark E. Stidham

IPC: H01L27/04 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/265 ,  H01L27/06 ,  H01L27/08 ,  H01L27/092

CPC classification number: H01L21/76224 ,  H01L21/26506 ,  H01L21/823892 ,  H01L27/04 ,  H01L27/0623 ,  H01L27/0635 ,  H01L27/0802 ,  H01L27/0811 ,  H01L27/0928

Abstract: A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a bipolar transistor device and triple well, a third region having a third resistivity, with a high resistivity for a passive device, a fourth region, substantially without implantation, to provide low perimeter capacitance for devices.

Abstract translation: 衬底包括具有第一电阻率的第一区域，用于优化场效应晶体管，具有第二电阻率的第二区域，用于优化双极晶体管器件和三阱的npn子集电极，具有第三电阻率的第三区域，具有第三电阻率 用于无源器件的高电阻率，第四区域，基本上没有植入，以为器件提供低周边电容。