公开(公告)号：US20210391473A1

公开(公告)日：2021-12-16

申请号：US16901852

申请日：2020-06-15

Applicant: International Business Machines Corporation

Inventor： Kai Zhao ,  Shahab Siddiqui ,  Daniel James Dechene ,  Rishikesh Krishnan ,  Charlotte DeWan Adams

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L21/8234

Abstract: Epitaxially grow first lower source-drain regions within a substrate. Portions of the substrate adjacent the lower regions are doped to form second lower source-drain regions. An undoped silicon layer is formed over the first and second lower regions. Etch completely through the undoped layer into the first and second lower regions to form fins and to define bottom junctions beneath the fins. The fins and bottom junctions define intermediate cavities. Form lower spacers, gates, and upper spacers in the cavities; form top junctions on outer surfaces of the fins; and form epitaxially grown first upper source-drain regions outward of the upper spacers and opposite the first lower regions. The first upper regions are doped the same as the first lower regions. Form second upper source-drain regions outward of the upper spacers and opposite the second lower regions; these are doped the same as the second lower regions.

公开(公告)号：US20180026035A1

公开(公告)日：2018-01-25

申请号：US15723283

申请日：2017-10-03

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Unoh Kwon ,  Kai Zhao

IPC: H01L27/092 ,  H01L29/51 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823842 ,  H01L29/42372 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517

Abstract: A semiconductor device includes a first transistor formed on a substrate, the first transistor including a channel region positioned on the substrate; a second transistor formed on the substrate, the second transistor including a channel region positioned on the substrate; a high-k dielectric layer disposed on the channel region of the first transistor and the channel region of the second transistor; a first transistor metal gate positioned in contact with the high-k dielectric on the first transistor; a second transistor metal gate positioned in contact with the high-k dielectric on the second transistor; an oxygen absorbing barrier disposed in contact with the high-k dielectric between the first transistor and the second transistor; and a conductive electrode material disposed on the first transistor, the second transistor, and the oxygen absorbing barrier.

公开(公告)号：US20160079394A1

公开(公告)日：2016-03-17

申请号：US14484916

申请日：2014-09-12

Applicant: International Business Machines Corporation

Inventor： Hongmei Li ,  Junjun Li ,  Xiaoping Liang ,  Kai Zhao

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/785 ,  H01L29/78696

Abstract: Methods to fabricate a stacked nanowire field effect transistor (FET) with reduced gate resistance are provided. The nanowire stack in the stacked nanowire FET can be provided by first forming a material stack of alternating sacrificial material layers and nanowire material layer. The sacrificial material layers and selected nanowire material layers in the material stack are subsequently removed to increase a vertical distance between two active nanowire material layers.

Abstract translation: 提供了制造具有降低的栅极电阻的堆叠的纳米线场效应晶体管（FET）的方法。 可以通过首先形成交替的牺牲材料层和纳米线材料层的材料堆叠来提供堆叠的纳米线FET中的纳米线堆叠。 随后去除材料堆叠中的牺牲材料层和选定的纳米线材料层以增加两个活性纳米线材料层之间的垂直距离。

公开(公告)号：US09287185B1

公开(公告)日：2016-03-15

申请号：US14753771

申请日：2015-06-29

Applicant: International Business Machines Corporation

Inventor： Griselda Bonilla ,  Baozhen Li ,  Barry P. Linder ,  James H. Stathis ,  Ernest Y. Wu ,  Kai Zhao

IPC: H01L21/00 ,  H01L21/66 ,  G01R31/28

CPC classification number: H01L22/14 ,  G01R31/2894 ,  H01L22/20

Abstract: Methods and systems determine an original statistical variance of an original failure distribution of a component (that is common to all chips tested) that occurs during manufacturing of wafers containing such chips. These methods and systems determine a first statistical variance of a reconstructed failure distribution, relative to sample size; and determine a second statistical variance of a mean time to failure of the component, relative to sample size. The first and second statistical variances are combined into a total reconstruction variance. Methods and systems determine whether the original statistical variance is less than the total reconstruction variance to identify whether the process of creating the reconstructed failure distribution can be used. Therefore, these methods and systems prohibit testing of the additional wafers manufactured using the specific wafer design and manufacturing process when on the original statistical variance is less than the total reconstruction variance.

Abstract translation: 方法和系统确定在制造包含这种芯片的晶片期间发生的组件的原始故障分布的原始统计方差（对于所有测试的芯片是常见的）。 这些方法和系统相对于样本大小确定重建失效分布的第一统计方差; 并且相对于样本大小确定组件的平均故障时间的第二统计方差。 第一和第二统计学差异被组合成总重建方差。 方法和系统确定原始统计方差是否小于总重建方差，以确定是否可以使用创建重建失效分布的过程。 因此，当原始统计方差小于总重建方差时，这些方法和系统禁止使用特定晶片设计和制造过程制造的附加晶片的测试。

公开(公告)号：US20240113200A1

公开(公告)日：2024-04-04

申请号：US17960116

申请日：2022-10-04

Applicant: International Business Machines Corporation

Inventor： HUIMEI ZHOU ,  MIAOMIAO WANG ,  Julien Frougier ,  Andrew M. Greene ,  Barry Paul Linder ,  Kai Zhao ,  Ruilong Xie ,  Tian Shen ,  Veeraraghavan S. Basker

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/66553 ,  H01L21/76831 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/66545

Abstract: An integrated circuit apparatus includes a substrate and a well contact that is disposed on the substrate. The well contact includes first and second source/drain structures that are disposed on the substrate; a metal vertical portion that contacts the substrate immediately between the first and second source/drain structures; inner spacers that electrically insulate the vertical portion from the adjacent source/drain structures; bottom dielectric isolation that electrically insulates the source/drain structures from the substrate; and a well portion that is embedded into the substrate in registry with the vertical portion. The well portion is doped differently than the substrate.

公开(公告)号：US20230386897A1

公开(公告)日：2023-11-30

申请号：US17664671

申请日：2022-05-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Oleg Gluschenkov ,  Yasir Sulehria ,  Ruilong Xie ,  Kai Zhao

IPC: H01L21/768 ,  H01L21/311 ,  H01L29/40 ,  H01L29/417 ,  H01L23/522

CPC classification number: H01L21/76804 ,  H01L21/311 ,  H01L29/401 ,  H01L29/41725 ,  H01L23/5226 ,  H01L29/0847

Abstract: A microelectronics device including a gate region located adjacent to a source/drain region. A contact located above the source/drain region, where the contact has a bottom section, a middle section and top section, wherein the sidewalls of the bottom section, the middle section, and the top section of the contact are tapered towards a center Y-axis of the contact. A gate contact located above the gate region, where the gate contact has tapered sidewalls towards a center Y-axis of the gate contact. The gate contact is adjacent to the contact. The tapering of the sidewalls of the gate contact is inverse to the tapering of the sidewalls of the contact.

公开(公告)号：US20210217873A1

公开(公告)日：2021-07-15

申请号：US16742295

申请日：2020-01-14

Applicant: International Business Machines Corporation

Inventor： Shahab Siddiqui ,  Koji Watanabe ,  Charlotte DeWan Adams ,  Kai Zhao ,  Daniel James Dechene ,  Rishikesh Krishnan

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8234

Abstract: A method of forming a semiconductor structure includes forming a first nanosheet stack and a second nanosheet stack on a semiconductor substrate. The first nanosheet stack includes a plurality of alternating first sacrificial layers and first channel layers. The first sacrificial layers each define a first sacrificial height. The second nanosheet stack includes a plurality of alternating second sacrificial layers and second channel layers. The second sacrificial layers each define a second sacrificial height greater than the first sacrificial height of the first sacrificial layers. The method further includes removing the first and second sacrificial layers respectively from the first and second nanosheet stacks. A metal gate is deposited over the first and second nanosheet stacks to form respective first and second nanosheet transistor structures.

公开(公告)号：US09818746B2

公开(公告)日：2017-11-14

申请号：US14994650

申请日：2016-01-13

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Unoh Kwon ,  Kai Zhao

IPC: H01L21/70 ,  H01L27/092 ,  H01L29/49 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823842 ,  H01L29/42372 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517

Abstract: A semiconductor device includes a first transistor formed on a substrate, the first transistor including a channel region positioned on the substrate; a second transistor formed on the substrate, the second transistor including a channel region positioned on the substrate; a high-k dielectric layer disposed on the channel region of the first transistor and the channel region of the second transistor; a first transistor metal gate positioned in contact with the high-k dielectric on the first transistor; a second transistor metal gate positioned in contact with the high-k dielectric on the second transistor; an oxygen absorbing barrier disposed in contact with the high-k dielectric between the first transistor and the second transistor; and a conductive electrode material disposed on the first transistor, the second transistor, and the oxygen absorbing barrier.

公开(公告)号：US20240419882A1

公开(公告)日：2024-12-19

申请号：US18333685

申请日：2023-06-13

Applicant: International Business Machines Corporation

Inventor： Xiaoming Yang ,  SOMNATH GHOSH ,  Huai Huang ,  Yann Mignot ,  Kai Zhao ,  Daniel Charles Edelstein

IPC: G06F30/39

Abstract: Embodiments of the invention are directed to a computer system having a processor communicatively coupled to a memory. The processor performs processor operations that include accessing an electronic file that includes an electronic integrated circuit (IC) design. The electronic file is operable to control a fabrication system to fabricate an IC according to the electronic IC design. The processor operations further includes applying a bulging predication analysis to the electronic IC design; and making one or more changes to the electronic IC design based at least in part on a result of the bulging prediction analysis.

公开(公告)号：US20230378258A1

公开(公告)日：2023-11-23

申请号：US17663676

申请日：2022-05-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Anthony I. Chou ,  Brent A. Anderson ,  John Christopher Arnold ,  Junli Wang ,  Kai Zhao ,  Terence Hook ,  Julien Frougier ,  Xuefeng Liu

IPC: H01L29/06 ,  H01L21/768 ,  H01L21/02 ,  H01L21/74

CPC classification number: H01L29/0665 ,  H01L21/76898 ,  H01L21/0237 ,  H01L21/0259 ,  H01L21/76829 ,  H01L21/743

Abstract: A method including forming an oxide layer on a first substrate and forming a second substrate on the oxide layer. Doping a first section of the second substrate while not doping a second section of the second substrate. Forming a first nano device on the second section of the second substrate and forming a second nano device on first section of the second substrate. Flipping the first substrate over to allow for backside processing of the substrate and forming at least one backside contact connected to the first nano device while backside contacts are not formed or connected to the second nano device.