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    REDUCING UNCORRECTABLE ERRORS BASED ON A HISTORY OF CORRECTABLE ERRORS
    11.
    发明申请
    REDUCING UNCORRECTABLE ERRORS BASED ON A HISTORY OF CORRECTABLE ERRORS 有权

    公开(公告)号：US20170091023A1

    公开(公告)日：2017-03-30

    申请号：US14870347

    申请日：2015-09-30

    Applicant: International Business Machines Corporation

    Inventor： Glenn D. Gilda ,  Patrick J. Meaney

    IPC: G06F11/10 ,  G11C29/52

    CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G06F11/106 ,  G11C29/44 ,  G11C29/52

    Abstract: In some embodiments, a computer-implemented method includes maintaining two or more error indicators for correctable errors occurring at two or more memory components. Each of the error indicators may be associated with a corresponding memory component. A correctable error may be detected as occurring during a first memory fetch operation at a first memory component. A first error indicator corresponding to the first memory component may be set, responsive to the correctable error at the first memory component. An uncorrectable error may be detected during a second memory fetch operation. It may be detected that the first error indicator is set. The first memory component may be marked, responsive to the uncorrectable error and to detecting that the first error indicator is set. The two or more error indicators for correctable errors may thus determine which memory component to mark due to the uncorrectable error.

    Reestablishing synchronization in a memory system
    13.
    发明授权
    Reestablishing synchronization in a memory system 有权
    重新建立内存系统中的同步

    公开(公告)号：US09535778B2

    公开(公告)日：2017-01-03

    申请号：US13835258

    申请日：2013-03-15

    Applicant: International Business Machines Corporation

    Inventor： Glenn D. Gilda ,  Patrick J. Meaney ,  Vesselina K. Papazova ,  John S. Dodson

    IPC: G06F11/07 ,  G06F1/12 ,  G06F11/10 ,  G06F11/14 ,  G06F11/20 ,  G06F11/16

    CPC classification number: G06F11/1662 ,  G06F1/04 ,  G06F1/10 ,  G06F1/12 ,  G06F3/0614 ,  G06F3/0619 ,  G06F3/0629 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0683 ,  G06F11/0757 ,  G06F11/1044 ,  G06F11/141 ,  G06F11/1604 ,  G06F11/1666 ,  G06F11/20 ,  G06F11/2007 ,  G06F13/1673

    Abstract: Embodiments relate to reestablishing synchronization across multiple channels in a memory system. One aspect is a system that includes a plurality of channels, each providing communication with a memory buffer chip and a plurality of memory devices. A memory control unit is coupled to the plurality of channels. The memory control unit is configured to perform a method that includes receiving an out-of-synchronization indication associated with at least one of the channels. The memory control unit performs a first stage of reestablishing synchronization that includes selectively stopping new traffic on the plurality of channels, waiting for a first time period to expire, resuming traffic on the plurality of channels based on the first time period expiring, and verifying that synchronization is reestablished for a second time period.

    Abstract translation: 实施例涉及重新建立在存储器系统中的多个通道之间的同步。 一个方面是包括多个通道的系统，每个通道提供与存储器缓冲器芯片和多个存储器件的通信。 存储器控制单元耦合到多个通道。 存储器控制单元被配置为执行包括接收与至少一个信道相关联的失步指示的方法。 存储器控制单元执行重新建立同步的第一阶段，其包括选择性地停止多个信道上的新业务，等待第一时间段到期，基于第一时间段到期，恢复多个信道上的业务，并验证 同步在第二时间段重新建立。

    Reestablishing synchronization in a memory system
    14.
    发明授权
    Reestablishing synchronization in a memory system 有权
    重新建立内存系统中的同步

    公开(公告)号：US09495231B2

    公开(公告)日：2016-11-15

    申请号：US15072659

    申请日：2016-03-17

    Applicant: International Business Machines Corporation

    Inventor： Glenn D. Gilda ,  Patrick J. Meaney ,  Vesselina K. Papazova ,  John S. Dodson

    IPC: G06F1/12 ,  G06F11/10 ,  G06F11/14 ,  G06F11/16 ,  G06F11/20 ,  G06F11/07

    CPC classification number: G06F11/1662 ,  G06F1/04 ,  G06F1/10 ,  G06F1/12 ,  G06F3/0614 ,  G06F3/0619 ,  G06F3/0629 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0683 ,  G06F11/0757 ,  G06F11/1044 ,  G06F11/141 ,  G06F11/1604 ,  G06F11/1666 ,  G06F11/20 ,  G06F11/2007 ,  G06F13/1673

    Abstract: Embodiments relate to reestablishing synchronization across multiple channels in a memory system. One aspect is a system that includes a plurality of channels, each providing communication with a memory buffer chip and a plurality of memory devices. A memory control unit is coupled to the plurality of channels. The memory control unit is configured to perform a method that includes receiving an out-of-synchronization indication associated with at least one of the channels. The memory control unit performs a first stage of reestablishing synchronization that includes selectively stopping new traffic on the plurality of channels, waiting for a first time period to expire, resuming traffic on the plurality of channels based on the first time period expiring, and verifying that synchronization is reestablished for a second time period.

    Abstract translation: 实施例涉及重新建立在存储器系统中的多个通道之间的同步。 一个方面是包括多个通道的系统，每个通道提供与存储器缓冲器芯片和多个存储器件的通信。 存储器控制单元耦合到多个通道。 存储器控制单元被配置为执行包括接收与至少一个信道相关联的失步指示的方法。 存储器控制单元执行重新建立同步的第一阶段，其包括选择性地停止多个信道上的新业务，等待第一时间段到期，基于第一时间段到期，恢复多个信道上的业务，并验证 同步在第二时间段重新建立。

    Combined rank and linear address incrementing utility for computer memory test operations
    15.
    发明授权
    Combined rank and linear address incrementing utility for computer memory test operations 有权
    用于计算机内存测试操作的组合级和线性地址递增实用程序

    公开(公告)号：US09437327B2

    公开(公告)日：2016-09-06

    申请号：US15063727

    申请日：2016-03-08

    Applicant: International Business Machines Corporation

    Inventor： Lawrence D. Curley ,  Patrick J. Meaney ,  George C. Wellwood

    IPC: G11C29/10 ,  G06F11/263 ,  G06F11/07

    CPC classification number: G11C29/10 ,  G06F11/0727 ,  G06F11/0787 ,  G06F11/2635 ,  G06F12/0607 ,  G11C5/04 ,  G11C29/18 ,  G11C29/20 ,  G11C2029/0409 ,  G11C2029/1806

    Abstract: Embodiments include a combined rank and linear memory address incrementing utility. An aspect includes an address incrementing utility suitable for implementation within a memory controller as an integrated subsystem of a central processing unit (CPU) chip. In this type of on-chip embodiment, the address incrementing utility utilizes dedicated hardware, chip-resident firmware, and one or more memory address configuration maps to enhance processing speed, efficiency and accuracy. The combined rank and linear memory address incrementing utility is designed to efficiently increment through all of the individual bit addresses for a large logical memory space divided into a number of ranks on a rank-by-rank basis. The address incrementing utility sequentially generates all of the sequential memory addresses for a selected rank, and then moves to the next rank and sequentially generates all of the memory addresses for that rank, and so forth until of the ranks have been processed.

    Abstract translation: 实施例包括组合的等级和线性存储器地址递增实用程序。 一个方面包括适用于作为中央处理单元（CPU）芯片的集成子系统的存储器控​​制器内实现的地址递增实用程序。 在这种片上实施例中，地址递增实用程序利用专用硬件，驻留芯片的固件和一个或多个存储器地址配置图来提高处理速度，效率和精度。 组合的等级和线性存储器地址递增实用程序被设计为有效地递增遍历所有单个位地址，以便逐级地划分为多个等级的大逻辑存储器空间。 地址增加实用程序顺序地产生所选择的等级的所有顺序存储器地址，然后移动到下一个级别并且顺序地产生该等级的所有存储器地址，并且等等，直到等级被处理。

    BITLINE DELETION
    18.
    发明申请
    BITLINE DELETION 有权

    公开(公告)号：US20130339809A1

    公开(公告)日：2013-12-19

    申请号：US13788744

    申请日：2013-03-07

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Ekaterina M. Ambroladze ,  Michael A. Blake ,  Michael Fee ,  Hieu T. Huynh ,  Patrick J. Meaney ,  Arthur J. O'Neill

    IPC: G06F11/08

    CPC classification number: G06F11/1064 ,  G06F11/073 ,  G06F11/076 ,  G06F11/08 ,  G11C2029/1204

    Abstract: Embodiments relate to a computer system for bitline deletion, the system including a cache controller and cache. The system is configured to perform a method including detecting a first error when reading a first cache line, recording a first address of the first error, detecting a second error when reading a second cache line, recording a second address of the second error, comparing first and second bitline addresses, comparing the first and second wordline address, activating a bitline delete mode based on matching first and second bitline addresses and not matching first and second wordline addresses, detecting a third error when reading a third cache line, recording a third bitline address of the third error, comparing the second bitline address to the third bitline address and deleting a location corresponding to the third cache line based on the activated bitline delete mode and matching third and second bitline addresses.

    Abstract translation: 实施例涉及用于位线删除的计算机系统，该系统包括高速缓存控制器和高速缓存。 该系统被配置为执行一种方法，包括当读取第一高速缓存线时检测第一错误，记录第一错误的第一地址，在读取第二高速缓存行时检测第二错误，记录第二错误的第二地址，比较 第一和第二位线地址，比较第一和第二字线地址，基于匹配的第一和第二位线地址激活位线删除模式，并且不匹配第一和第二字线地址，在读取第三高速缓存线时检测第三错误，记录第三位线地址 将第二位线地址与第三位线地址进行比较，并且基于激活的位线删​​除模式和匹配的第三和第二位线地址来删除与第三高速缓存线对应的位置。

    CHANNEL MARKING FOR CHIP MARK OVERFLOW AND CALIBRATION ERRORS
    19.
    发明申请
    CHANNEL MARKING FOR CHIP MARK OVERFLOW AND CALIBRATION ERRORS 有权
    CHANNEL MARKING FOR CHIP MARK OVERFLOW和CALIBRATION ERRORS

    公开(公告)号：US20130047040A1

    公开(公告)日：2013-02-21

    申请号：US13658148

    申请日：2012-10-23

    Applicant: International Business Machines Corporation

    Inventor： Judy S. Johnson ,  Luis A. Lastras-Montano ,  Patrick J. Meaney ,  Eldee Stephens

    IPC: G06F11/30

    CPC classification number: G11C29/44 ,  G06F11/1044 ,  G06F11/1076 ,  G06F11/30 ,  G06F2211/1064

    Abstract: Marking memory chips as faulty when a fault is detected in data from the memory chip. Upon detecting that a plurality of memory chips are faulty, determining which of a plurality of memory channels contains the faulty memory chips. Marking one of a plurality of memory channels as failing in response to determining that the number of failing memory chips has exceeded a threshold.

    Abstract translation: 当从存储器芯片的数据中检测到故障时，将存储器芯片标记为故障。 在检测到多个存储器芯片有故障时，确定多个存储器通道中的哪一个存储有故障的存储器芯片。 响应于确定故障存储器芯片的数量已经超过阈值，将多个存储器通道中的一个标记为失败。

    Use of a cyclic redundancy code multiple-input shift register to provide early warning and fail detection
    20.
    发明授权
    Use of a cyclic redundancy code multiple-input shift register to provide early warning and fail detection 有权

    公开(公告)号：US11088782B2

    公开(公告)日：2021-08-10

    申请号：US16715162

    申请日：2019-12-16

    Applicant: International Business Machines Corporation

    Inventor： Steven R. Carlough ,  Patrick J. Meaney ,  Gary Van Huben

    IPC: H04L1/00 ,  H03M13/09

    Abstract: Aspects of the invention include using a cyclic redundancy code (CRC) multiple-input signature register (MISR) for early warning and fail detection. Received bits are monitored at a receiver for transmission errors. The monitoring includes receiving frames of bits that are a subset of frames of bits used by the transmitter to generate a multi-frame CRC. At least one of the received frames of bits includes payload bits and a source single check bit not included in the multi-frame CRC. It is determined whether a transmission error has occurred in the received frames of bits. The determining includes generating a calculated single check bit based at least in part on bits in the received frames of bits, and comparing the received source single check bit to the calculated single check bit. An error indication is transmitted to the transmitter if they don't match.

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