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    GENERATION OF MULTIPLE DIAMETER NANOWIRE FIELD EFFECT TRANSISTORS
    13.
    发明申请
    GENERATION OF MULTIPLE DIAMETER NANOWIRE FIELD EFFECT TRANSISTORS 审中-公开
    多直径纳米场效应晶体管的生成

    公开(公告)号：US20140239254A1

    公开(公告)日：2014-08-28

    申请号：US13864798

    申请日：2013-04-17

    Applicant: International Business Machines Corporation

    Inventor： Sarunya Bangsaruntip ,  Guy M. Cohen ,  Amlan Majumdar ,  Jeffrey W. Sleight

    IPC: H01L29/06 ,  H01L29/775

    CPC classification number: H01L29/0669 ,  B82Y10/00 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

    Abstract: A system is provided and includes a wafer and a mask. The wafer includes a silicon-on-insulator (SOI) structure disposed on a buried oxide (BOX) layer and has a first region with a first SOI thickness and a second region with a second SOI thickness, the first and second SOI thicknesses being different from one another and sufficiently large such that respective pairs of SOI pads connected via respective nanowires with different thicknesses are formable therein. The mask covers one of the first and second regions and prevents a thickness change of the other of the first and second regions from having effect at the one of the first and second regions.

    Abstract translation: 提供了一种系统，其包括晶片和掩模。 晶片包括设置在掩埋氧化物（BOX）层上的绝缘体上硅（SOI）结构，并且具有第一SOI厚度的第一区域和具有第二SOI厚度的第二区域，第一和第二SOI厚度不同 并且足够大，使得通过具有不同厚度的相应纳米线连接的各对SOI焊盘成为可能。 掩模覆盖第一和第二区域中的一个并且防止第一和第二区域中的另一个区域的厚度变化在第一和第二区域中的一个区域具有效果。

    Nanowire Capacitor for Bidirectional Operation
    14.
    发明申请
    Nanowire Capacitor for Bidirectional Operation 有权
    纳米线电容双向操作

    公开(公告)号：US20140209854A1

    公开(公告)日：2014-07-31

    申请号：US13751490

    申请日：2013-01-28

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Sarunya Bangsaruntip ,  Amlan Majumdar ,  Jeffrey W. Sleight

    IPC: H01L21/77 ,  H01L29/06

    CPC classification number: H01L21/77 ,  B82Y40/00 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1203 ,  H01L28/40 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/42392 ,  H01L29/458 ,  H01L29/66181 ,  H01L29/66439 ,  H01L29/665 ,  H01L29/775 ,  H01L29/78696 ,  H01L29/861 ,  H01L29/94 ,  Y10S977/762

    Abstract: A method of fabricating an electronic device includes the following steps. At least one first set and at least one second set of nanowires and pads are etched in an SOI layer of an SOI wafer. A first gate stack is formed that surrounds at least a portion of each of the first set of nanowires that serves as a channel region of a capacitor device. A second gate stack is formed that surrounds at least a portion of each of the second set of nanowires that serves as a channel region of a FET device. Source and drain regions of the FET device are selectively doped. A first silicide is formed on the source and drain regions of the capacitor device that extends at least to an edge of the first gate stack. A second silicide is formed on the source and drain regions of the FET device.

    Abstract translation: 一种制造电子装置的方法包括以下步骤。 在SOI晶片的SOI层中蚀刻至少一个第一组和至少一个第二组纳米线和衬垫。 形成第一栅极堆叠，其围绕用作电容器器件的沟道区域的第一组纳米线的每一个的至少一部分。 形成第二栅极堆叠，其围绕用作FET器件的沟道区域的第二组纳米线的每一个的至少一部分。 FET器件的源极和漏极区域被选择性地掺杂。 第一硅化物形成在至少延伸到第一栅极堆叠的边缘的电容器器件的源极和漏极区域上。 第二硅化物形成在FET器件的源极和漏极区域上。

    LOW LOSS CONDUCTIVE LINE USING BRIDGED CONDUCTOR
    18.
    发明申请
    LOW LOSS CONDUCTIVE LINE USING BRIDGED CONDUCTOR 有权

    公开(公告)号：US20210328125A1

    公开(公告)日：2021-10-21

    申请号：US16850862

    申请日：2020-04-16

    Applicant: International Business Machines Corporation

    Inventor： Salvatore Bernardo Olivadese ,  Sarunya Bangsaruntip ,  Daniela Florentina Bogorin ,  Nicholas Torleiv Bronn ,  Sean Hart ,  Patryk Gumann

    IPC: H01L39/02 ,  H01L39/24 ,  H01P3/02 ,  G06N10/00

    Abstract: Techniques for designing and fabricating quantum circuitry, including a coplanar waveguide (CPW), for quantum applications are presented. With regard to a CPW, a central conductor and two return conductor lines can be formed on a dielectric substrate, with one return conductor line on each side of the central conductor and separated from it by a space. The central conductor can have bridge portions that can be raised a desired distance above the substrate and base conductor portions situated between the bridge portions and in contact with the surface of the substrate; and/or portions of the substrate underneath the bridge portions of the central conductor can be removed such that the bridge portions, whether raised or unraised, can be the desired distance above the surface of the remaining substrate, and the base conductor portions can be in contact with other portions of the surface of the substrate that were not removed.

    Placement of carbon nanotube guided by DSA patterning
    19.
    发明授权
    Placement of carbon nanotube guided by DSA patterning 有权

    公开(公告)号：US10243156B2

    公开(公告)日：2019-03-26

    申请号：US15461175

    申请日：2017-03-16

    Applicant: International Business Machines Corporation

    Inventor： Ali Afzali-Ardakani ,  Sarunya Bangsaruntip ,  Shu-Jen Han ,  HsinYu Tsai

    IPC: H01L29/04 ,  H01L51/05 ,  H01L51/00

    Abstract: In one aspect, a method for placing carbon nanotubes on a dielectric includes: using DSA of a block copolymer to create a pattern in the placement guide layer on the dielectric which includes multiple trenches in the placement guide layer, wherein there is a first charge on sidewall and top surfaces of the trenches and a second charge on bottom surfaces of the trenches, and wherein the first charge is different from the second charge; and depositing a carbon nanotube solution onto the dielectric, wherein self-assembly of the deposited carbon nanotubes within the trenches occurs based on i) attractive forces between the first charge on the surfaces of the carbon nanotubes and the second charge on the bottom surfaces of the trenches and ii) repulsive forces between the first charge on the surfaces of the carbon nanotubes and the first charge on sidewall and top surfaces of the trenches.

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