-
公开(公告)号：US09019137B1
公开(公告)日：2015-04-28
申请号：US14158299
申请日：2014-01-17
发明人： Mikko Waltari , Michael Kappes
CPC分类号： H03M1/1245 , H03M1/804
摘要： A charge canceling multiplying digital-to-analog converter (MDAC) is provided with a reference block having inputs to accept reference voltages each sample clock cycle. The MDAC includes a sampling block having inputs to accept differential analog input voltage signals each sample clock cycle. A differential amplifier has a negative input and positive input connected to the reference block and sampling block to receive differential amplifier input signals, and a positive output and a negative output to supply differential output voltage signals each amplify clock cycle. The sampling section includes a first pair of feedback capacitors connected between the differential amplifier negative input and positive output, and a second pair of feedback capacitors connected between the differential amplifier positive input and negative output each amplify clock cycle. A capacitor from the first pair of parallel feedback capacitors is swapped with a capacitor from the second pair prior to each sample clock cycle.
摘要翻译： 电荷消除乘法数模转换器（MDAC）具有参考块，其具有输入以接受每个采样时钟周期的参考电压。 MDAC包括具有输入的采样块，每个采样时钟周期接受差分模拟输入电压信号。 差分放大器具有负输入和正输入，连接到参考块和采样块以接收差分放大器输入信号，以及正输出和负输出，以提供差分输出电压信号，每个放大时钟周期。 采样部分包括连接在差分放大器负输入和正输出之间的第一对反馈电容器，连接在差分放大器正输入和负输出之间的第二对反馈电容器每个放大时钟周期。 在每个采样时钟周期之前，来自第一对并联反馈电容器的电容器与来自第二对的电容器交换。
-
公开(公告)号：US08711026B1
公开(公告)日：2014-04-29
申请号：US14050434
申请日：2013-10-10
发明人： Michael Kappes
CPC分类号： H03M1/12 , H03M1/005 , H03M1/007 , H03M1/0643 , H03M1/1215 , H03M1/164 , H03M1/44 , H03M3/462
摘要： A data converter module is provided with an analog interface to receive analog signals, a digital interface to transmit digital signals, and a configuration interface to accept configuration signals. The data conversion module also includes a data conversion array (DCA) with selectively engageable data conversion circuits for the conversion of analog input signals to digital output signals, where the data conversion circuits are responsive to the configuration signals. The DCA's data conversion circuits include configurable data resolution circuits and configurable data conversion speed circuits. For example, the configurable data resolution circuits may be selected from averaging, oversampling, and multi-stage pipelining circuits. The DCA configurable data speed circuit may interleave the outputs from multiple parallelly connected ADCs operating at different clock phases. In one aspect, the number of clock phases is selectable. Also provided are methods for configurable data conversion.
摘要翻译： 数据转换器模块具有模拟接口以接收模拟信号，数字接口传输数字信号，配置接口接受配置信号。 数据转换模块还包括具有选择性地可接合的数据转换电路的数据转换阵列（DCA），用于将模拟输入信号转换成数字输出信号，其中数据转换电路响应于配置信号。 DCA的数据转换电路包括可配置数据分辨率电路和可配置数据转换速度电路。 例如，可以从平均，过采样和多级流水线电路中选择可配置的数据分辨率电路。 DCA可配置数据速度电路可以对来自在不同时钟阶段工作的多个并联连接的ADC的输出进行交织。 在一个方面，时钟相位的数量是可选择的。 还提供了可配置数据转换的方法。
-
公开(公告)号：US20140070859A1
公开(公告)日：2014-03-13
申请号：US14081568
申请日：2013-11-15
发明人： Mikko Waltari , Michael Kappes , William Huff
IPC分类号： H03L7/18
CPC分类号： H03L7/091 , H03L7/093 , H03L7/097 , H03L7/18 , H03L7/1806 , H03L2207/10 , H03L2207/50 , H03M1/0626 , H03M1/0836 , H03M1/12 , H03M1/1215 , H03M1/1245
摘要： A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency. A PLL using a voltage controlled oscillator (VCO) is one example of a frequency multiplier. The method samples the amplitude of the analog reference signal using the system clock signal and converts the sampled analog reference signal into a digitized reference signal. In response to comparing the digitized reference signal to an ideal digitized reference signal, the phase error correction for the system clock signal is derived. The phase error correction at a first instance of time can be applied to the digitized data signal, previously converted from an analog data signal sampled at a first instance of time with the system clock signal.
摘要翻译： 提供了一种用于倍频抖动校正的系统和方法。 该方法接受具有第一频率的模拟参考信号，并且使用模拟参考信号导出具有大于第一频率的第二频率的系统时钟信号。 使用压控振荡器（VCO）的PLL是倍频器的一个例子。 该方法使用系统时钟信号对模拟参考信号的振幅进行采样，并将采样的模拟参考信号转换为数字化参考信号。 响应于将数字化参考信号与理想数字化参考信号进行比较，导出系统时钟信号的相位误差校正。 在第一时刻的相位误差校正可以应用于数字化数据信号，该数字化数据信号是先前从系统时钟信号在第一时刻采样的模拟数据信号转换的。
-
公开(公告)号：US20150188558A1
公开(公告)日：2015-07-02
申请号：US14656880
申请日：2015-03-13
发明人： Michael Kappes
IPC分类号： H03M1/10
CPC分类号： H03M1/1071 , H03M1/005 , H03M1/12 , H03M1/66
摘要： A method is provided for supplying a customized data converter fabricated from a universal function die. The method initially fabricates a plurality of universal data converter dice. Each universal data converter die is capable of performing a first plurality of data conversion algorithms. After the dice are made, each universal data converter die is tested to verify the performance of the first plurality of data conversion algorithms. Subsequently, a request is received for a customized data converter capable of performing a first data conversion function, which is selected from among the first plurality of data conversion algorithms. The method then fabricates a customized data converter capable of performing the first data conversion function, using a tested universal data converter die. The unselected data converter functions are disabled (not enabled). A configuration interface may be used to enable the requested data conversion function.
摘要翻译： 提供了一种用于提供由通用功能模具制造的定制数据转换器的方法。 该方法最初制造了多个通用数据转换器骰子。 每个通用数据转换器管芯能够执行第一多个数据转换算法。 在制作骰子之后，测试每个通用数据转换器管芯以验证第一多个数据转换算法的性能。 随后，对于能够执行从第一多个数据转换算法中选择的第一数据转换功能的定制数据转换器，接收到请求。 然后，该方法使用测试的通用数据转换器芯片制造能够执行第一数据转换功能的定制数据转换器。 未选择的数据转换器功能被禁用（未启用）。 可以使用配置接口来启用所请求的数据转换功能。
-
公开(公告)号：US20150109038A1
公开(公告)日：2015-04-23
申请号：US14562914
申请日：2014-12-08
发明人： Mikko Waltari , Michael Kappes , William Huff
CPC分类号： H03L7/091 , H03L7/093 , H03L7/097 , H03L7/18 , H03L7/1806 , H03L2207/10 , H03L2207/50 , H03M1/0626 , H03M1/0836 , H03M1/12 , H03M1/1215 , H03M1/1245
摘要： A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency. A PLL using a voltage controlled oscillator (VCO) is one example of a frequency multiplier. The method samples the amplitude of the analog reference signal using the system clock signal and converts the sampled analog reference signal into a digitized reference signal. In response to comparing the digitized reference signal to an ideal digitized reference signal, the phase error correction for the system clock signal is derived. The phase error correction at a first instance of time can be applied to the digitized data signal, previously converted from an analog data signal sampled at a first instance of time with the system clock signal.
摘要翻译： 提供了一种用于倍频抖动校正的系统和方法。 该方法接受具有第一频率的模拟参考信号，并且使用模拟参考信号导出具有大于第一频率的第二频率的系统时钟信号。 使用压控振荡器（VCO）的PLL是倍频器的一个示例。 该方法使用系统时钟信号对模拟参考信号的振幅进行采样，并将采样的模拟参考信号转换为数字化参考信号。 响应于将数字化参考信号与理想数字化参考信号进行比较，导出系统时钟信号的相位误差校正。 在第一时刻的相位误差校正可以应用于数字化数据信号，该数字化数据信号是先前从系统时钟信号在第一时刻采样的模拟数据信号转换的。
-
16.发明授权System and method for customizing data converters from universal function dice 有权通用功能骰子定制数据转换器的系统和方法公开(公告)号：US09007243B2
公开(公告)日：2015-04-14
申请号：US14537587
申请日：2014-11-10
发明人： Michael Kappes
CPC分类号： H03M1/1071 , H03M1/005 , H03M1/12 , H03M1/66
摘要： A method is provided for supplying a customized data converter fabricated from a universal function die. The method initially fabricates a plurality of universal data converter dice. Each universal data converter die is capable of performing a first plurality of data conversion algorithms. After the dice are made, each universal data converter die is tested to verify the performance of the first plurality of data conversion algorithms. Subsequently, a request is received for a customized data converter capable of performing a first data conversion function, which is selected from among the first plurality of data conversion algorithms. The method then fabricates a customized data converter capable of performing the first data conversion function, using a tested universal data converter die. The unselected data converter functions are disabled (not enabled). A configuration interface may be used to enable the requested data conversion function.
摘要翻译： 提供了一种用于提供由通用功能模具制造的定制数据转换器的方法。 该方法最初制造了多个通用数据转换器骰子。 每个通用数据转换器管芯能够执行第一多个数据转换算法。 在制作骰子之后，测试每个通用数据转换器管芯以验证第一多个数据转换算法的性能。 随后，对于能够执行从第一多个数据转换算法中选择的第一数据转换功能的定制数据转换器，接收到请求。 然后，该方法使用测试的通用数据转换器芯片制造能够执行第一数据转换功能的定制数据转换器。 未选择的数据转换器功能被禁用（未启用）。 可以使用配置接口来启用所请求的数据转换功能。
-
公开(公告)号：US09007108B1
公开(公告)日：2015-04-14
申请号：US14562914
申请日：2014-12-08
发明人： Mikko Waltari , Michael Kappes , William Huff
CPC分类号： H03L7/091 , H03L7/093 , H03L7/097 , H03L7/18 , H03L7/1806 , H03L2207/10 , H03L2207/50 , H03M1/0626 , H03M1/0836 , H03M1/12 , H03M1/1215 , H03M1/1245
摘要： A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency. A PLL using a voltage controlled oscillator (VCO) is one example of a frequency multiplier. The method samples the amplitude of the analog reference signal using the system clock signal and converts the sampled analog reference signal into a digitized reference signal. In response to comparing the digitized reference signal to an ideal digitized reference signal, the phase error correction for the system clock signal is derived. The phase error correction at a first instance of time can be applied to the digitized data signal, previously converted from an analog data signal sampled at a first instance of time with the system clock signal.
摘要翻译： 提供了一种用于倍频抖动校正的系统和方法。 该方法接受具有第一频率的模拟参考信号，并且使用模拟参考信号导出具有大于第一频率的第二频率的系统时钟信号。 使用压控振荡器（VCO）的PLL是倍频器的一个例子。 该方法使用系统时钟信号对模拟参考信号的振幅进行采样，并将采样的模拟参考信号转换为数字化参考信号。 响应于将数字化参考信号与理想数字化参考信号进行比较，导出系统时钟信号的相位误差校正。 在第一时刻的相位误差校正可以应用于数字化数据信号，该数字化数据信号是先前从系统时钟信号在第一时间采样的模拟数据信号转换的。
-
公开(公告)号：US08878577B2
公开(公告)日：2014-11-04
申请号：US14081568
申请日：2013-11-15
发明人： Mikko Waltari , Michael Kappes , William Huff
CPC分类号： H03L7/091 , H03L7/093 , H03L7/097 , H03L7/18 , H03L7/1806 , H03L2207/10 , H03L2207/50 , H03M1/0626 , H03M1/0836 , H03M1/12 , H03M1/1215 , H03M1/1245
摘要： A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency. A PLL using a voltage controlled oscillator (VCO) is one example of a frequency multiplier. The method samples the amplitude of the analog reference signal using the system clock signal and converts the sampled analog reference signal into a digitized reference signal. In response to comparing the digitized reference signal to an ideal digitized reference signal, the phase error correction for the system clock signal is derived. The phase error correction at a first instance of time can be applied to the digitized data signal, previously converted from an analog data signal sampled at a first instance of time with the system clock signal.
摘要翻译： 提供了一种用于倍频抖动校正的系统和方法。 该方法接受具有第一频率的模拟参考信号，并且使用模拟参考信号导出具有大于第一频率的第二频率的系统时钟信号。 使用压控振荡器（VCO）的PLL是倍频器的一个例子。 该方法使用系统时钟信号对模拟参考信号的振幅进行采样，并将采样的模拟参考信号转换为数字化参考信号。 响应于将数字化参考信号与理想数字化参考信号进行比较，导出系统时钟信号的相位误差校正。 在第一时刻的相位误差校正可以应用于数字化数据信号，该数字化数据信号是先前从系统时钟信号在第一时刻采样的模拟数据信号转换的。
-
公开(公告)号：US08760335B1
公开(公告)日：2014-06-24
申请号：US14164369
申请日：2014-01-27
发明人： Michael Kappes
IPC分类号： H03M1/12
CPC分类号： H03M1/12 , H03M1/005 , H03M1/007 , H03M1/0643 , H03M1/1215 , H03M1/164 , H03M1/44 , H03M3/462
摘要： A data converter module is provided with an analog interface to receive analog signals, a digital interface to transmit digital signals, and a configuration interface to accept configuration signals. The data conversion module also includes a data conversion array (DCA) with selectively engageable data conversion circuits for the conversion of analog input signals to digital output signals, where the data conversion circuits are responsive to the configuration signals. The DCA's data conversion circuits include configurable data resolution circuits and configurable data conversion speed circuits. For example, the configurable data resolution circuits may be selected from averaging, oversampling, and multi-stage pipelining circuits. The DCA configurable data speed circuit may interleave the outputs from multiple parallelly connected ADCs operating at different clock phases. In one aspect, the number of clock phases is selectable. Also provided are methods for configurable data conversion.
摘要翻译： 数据转换器模块具有模拟接口以接收模拟信号，数字接口传输数字信号，配置接口接受配置信号。 数据转换模块还包括具有选择性地可接合的数据转换电路的数据转换阵列（DCA），用于将模拟输入信号转换成数字输出信号，其中数据转换电路响应于配置信号。 DCA的数据转换电路包括可配置数据分辨率电路和可配置数据转换速度电路。 例如，可以从平均，过采样和多级流水线电路中选择可配置数据分辨率电路。 DCA可配置数据速度电路可以对来自在不同时钟阶段工作的多个并联连接的ADC的输出进行交织。 在一个方面，时钟相位的数量是可选择的。 还提供了可配置数据转换的方法。
-
-
-
-
-
-
-
-
搜索结果
19 条记录 (耗时 0.026 秒)
