公开(公告)号：US09923066B2

公开(公告)日：2018-03-20

申请号：US15221122

申请日：2016-07-27

Applicant: Infineon Technologies AG

Inventor： Daniel Kueck ,  Thomas Aichinger ,  Franz Hirler ,  Anton Mauder

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/739 ,  H01L29/10 ,  H01L29/423 ,  H01L29/06 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L29/408 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813

Abstract: A semiconductor device includes a source zone electrically connected to a first load terminal, a contiguous zone isolating the source zone from a drift zone, and a trench extending into a semiconductor body along a vertical direction and including a first electrode electrically connected to a control terminal and an insulator in contact with the contiguous zone and which isolates the first electrode from the semiconductor body. The insulator has, at a trench bottom region, a first thickness along the vertical direction, and, at a trench top region, a second thickness along a lateral direction, the first thickness being greater than the second thickness by a factor of at least 1.5. The contiguous zone is arranged in contact with the insulator and extends further along the vertical direction than the trench, and the trench bottom region and the contiguous zone overlap along the lateral direction.

公开(公告)号：US09923053B2

公开(公告)日：2018-03-20

申请号：US15400299

申请日：2017-01-06

Applicant: Infineon Technologies AG

Inventor： Romain Esteve ,  Dethard Peters ,  Wolfgang Bergner ,  Ralf Siemieniec ,  Thomas Aichinger ,  Daniel Kueck

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/16 ,  H01L29/10 ,  H01L29/78 ,  H01L29/423 ,  H01L21/04 ,  H01L29/66

Abstract: A SIC transistor device includes a silicon-carbide semiconductor substrate having a plurality of first doped regions laterally spaced apart from one another and beneath a main surface of the substrate, a second doped region extending from the main surface to a third doped region that is above the first doped regions, and a plurality of fourth doped regions in the substrate extending from the main surface to the first doped regions. The second doped region has a first conductivity type. The first, third and fourth doped regions have a second conductivity type opposite the first conductivity type. A gate trench extends through the second and third doped regions. The gate trench has sidewalls, a bottom and rounded corners between the bottom and the sidewalls.

公开(公告)号：US20170345905A1

公开(公告)日：2017-11-30

申请号：US15162716

申请日：2016-05-24

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Dethard Peters ,  Romain Esteve ,  Wolfgang Bergner ,  Thomas Aichinger ,  Daniel Kueck ,  Roland Rupp ,  Bernd Zippelius ,  Karlheinz Feldrapp ,  Christian Strenger

IPC: H01L29/423 ,  H01L29/739 ,  H01L29/20 ,  H01L29/16 ,  H01L29/10 ,  H01L29/78 ,  H01L29/04

CPC classification number: H01L29/4236 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/407 ,  H01L29/66068 ,  H01L29/7397 ,  H01L29/7827

Abstract: A semiconductor device includes trench gate structures extending from a first surface into a semiconductor body from a wide-bandgap semiconductor material. The trench gate structures separate mesa portions of the semiconductor body from each other. In the mesa portions, body regions form first pn junctions with a drain structure and directly adjoin first mesa sidewalls. Source regions in the mesa portions form second pn junctions with the body regions, wherein the body regions separate the source regions from the drain structure. The source regions directly adjoin the first mesa sidewalls and second mesa sidewalls opposite to the first mesa sidewalls.

公开(公告)号：US20170117352A1

公开(公告)日：2017-04-27

申请号：US15400299

申请日：2017-01-06

Applicant: Infineon Technologies AG

Inventor： Romain Esteve ,  Dethard Peters ,  Wolfgang Bergner ,  Ralf Siemieniec ,  Thomas Aichinger ,  Daniel Kueck

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/423 ,  H01L21/04 ,  H01L29/16 ,  H01L29/78

CPC classification number: H01L29/063 ,  H01L21/02236 ,  H01L21/045 ,  H01L21/0465 ,  H01L21/0475 ,  H01L21/049 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/324 ,  H01L21/3247 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/7813

Abstract: A SIC transistor device includes a silicon-carbide semiconductor substrate having a plurality of first doped regions laterally spaced apart from one another and beneath a main surface of the substrate, a second doped region extending from the main surface to a third doped region that is above the first doped regions, and a plurality of fourth doped regions in the substrate extending from the main surface to the first doped regions. The second doped region has a first conductivity type. The first, third and fourth doped regions have a second conductivity type opposite the first conductivity type. A gate trench extends through the second and third doped regions. The gate trench has sidewalls, a bottom and rounded corners between the bottom and the sidewalls.

公开(公告)号：US11101343B2

公开(公告)日：2021-08-24

申请号：US16404284

申请日：2019-05-06

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Thomas Aichinger ,  Thomas Basler ,  Wolfgang Bergner ,  Rudolf Elpelt ,  Romain Esteve ,  Michael Hell ,  Daniel Kueck ,  Caspar Leendertz ,  Dethard Peters ,  Hans-Joachim Schulze

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/16 ,  H01L21/04 ,  H01L29/66 ,  H01L29/10

Abstract: A semiconductor component has a gate structure that extends from a first surface into an SiC semiconductor body. A body area in the SiC semiconductor body adjoins a first side wall of the gate structure. A first shielding area and a second shielding area of the conductivity type of the body area have at least twice as high a level of doping as the body area. A diode area forms a Schottky contact with a load electrode between the first shielding area and the second shielding area.

公开(公告)号：US10217636B2

公开(公告)日：2019-02-26

申请号：US15919918

申请日：2018-03-13

Applicant: Infineon Technologies AG

Inventor： Thomas Aichinger ,  Victorina Poenariu ,  Wolfgang Bergner ,  Romain Esteve ,  Daniel Kueck ,  Dethard Peters ,  Gerald Reinwald ,  Roland Rupp ,  Gerald Unegg

IPC: H01L29/16 ,  H01L29/66 ,  H01L21/02 ,  H01L21/04 ,  H01L29/10 ,  H01L29/78 ,  H01L29/40 ,  H01L29/861 ,  H01L29/06 ,  H01L21/3065 ,  H01L29/423

Abstract: A trench is formed that extends from a main surface into a crystalline silicon carbide semiconductor layer. A mask is formed that includes a mask opening exposing the trench and a rim section of the main surface around the trench. By irradiation with a particle beam a first portion of the semiconductor layer exposed by the mask opening and a second portion outside of the vertical projection of the mask opening and directly adjoining to the first portion are amorphized. A vertical extension of the amorphized second portion gradually decreases with increasing distance to the first portion. The amorphized first and second portions are removed.

公开(公告)号：US20180204725A1

公开(公告)日：2018-07-19

申请号：US15919918

申请日：2018-03-13

Applicant: Infineon Technologies AG

Inventor： Thomas Aichinger ,  Victorina Poenariu ,  Wolfgang Bergner ,  Romain Esteve ,  Daniel Kueck ,  Dethard Peters ,  Gerald Reinwald ,  Roland Rupp ,  Gerald Unegg

IPC: H01L21/04 ,  H01L29/861 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/40 ,  H01L21/3065 ,  H01L29/16 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L21/0475 ,  H01L21/049 ,  H01L21/3065 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66068 ,  H01L29/7813 ,  H01L29/8613

Abstract: A trench is formed that extends from a main surface into a crystalline silicon carbide semiconductor layer. A mask is formed that includes a mask opening exposing the trench and a rim section of the main surface around the trench. By irradiation with a particle beam a first portion of the semiconductor layer exposed by the mask opening and a second portion outside of the vertical projection of the mask opening and directly adjoining to the first portion are amorphized. A vertical extension of the amorphized second portion gradually decreases with increasing distance to the first portion. The amorphized first and second portions are removed.

公开(公告)号：US20180158920A1

公开(公告)日：2018-06-07

申请号：US15866755

申请日：2018-01-10

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Dethard Peters ,  Romain Esteve ,  Wolfgang Bergner ,  Thomas Aichinger ,  Daniel Kueck ,  Roland Rupp ,  Bernd Zippelius ,  Karlheinz Feldrapp ,  Christian Strenger

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/739 ,  H01L29/10 ,  H01L29/20 ,  H01L29/04 ,  H01L29/16

CPC classification number: H01L29/4236 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/407 ,  H01L29/7397 ,  H01L29/7827

Abstract: A semiconductor device includes a semiconductor body formed from a semiconductor material with a band-gap of at least 2.0 eV, the semiconductor body having a diode region and a source region. The semiconductor device further includes a trench gate structure having a first sidewall and a second sidewall opposite the first sidewall, the first sidewall and the second sidewall extending along a common longitudinal direction. A doping concentration of a first doping type is higher in the diode region than in the source region. The trench gate structure projects from a first surface of the semiconductor body into the semiconductor body. A first portion of the second sidewall at the first surface is directly adjoined by the source region. A second portion of the second sidewall is in direct contact with the diode region. Additional semiconductor device embodiments are provided.

公开(公告)号：US09960230B2

公开(公告)日：2018-05-01

申请号：US15400299

申请日：2017-01-06

Applicant: Infineon Technologies AG

Inventor： Romain Esteve ,  Dethard Peters ,  Wolfgang Bergner ,  Ralf Siemieniec ,  Thomas Aichinger ,  Daniel Kueck

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/16 ,  H01L29/10 ,  H01L29/78 ,  H01L29/423 ,  H01L21/04 ,  H01L29/66

CPC classification number: H01L29/063 ,  H01L21/02236 ,  H01L21/045 ,  H01L21/0465 ,  H01L21/0475 ,  H01L21/049 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/324 ,  H01L21/3247 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/7813

Abstract: A SIC transistor device includes a silicon-carbide semiconductor substrate having a plurality of first doped regions laterally spaced apart from one another and beneath a main surface of the substrate, a second doped region extending from the main surface to a third doped region that is above the first doped regions, and a plurality of fourth doped regions in the substrate extending from the main surface to the first doped regions. The second doped region has a first conductivity type. The first, third and fourth doped regions have a second conductivity type opposite the first conductivity type. A gate trench extends through the second and third doped regions. The gate trench has sidewalls, a bottom and rounded corners between the bottom and the sidewalls.

公开(公告)号：US09543414B2

公开(公告)日：2017-01-10

申请号：US14567504

申请日：2014-12-11

Applicant: Infineon Technologies AG

Inventor： Romain Esteve ,  Dethard Peters ,  Wolfgang Bergner ,  Ralf Siemieniec ,  Thomas Aichinger ,  Daniel Kueck

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/423 ,  H01L21/324 ,  H01L21/04 ,  H01L21/02 ,  H01L21/311 ,  H01L29/16

Abstract: A silicon-carbide semiconductor substrate having a plurality of first doped regions being laterally spaced apart from one another and beneath a main surface, and a second doped region extending from the main surface to a third doped region that is above the first doped regions is formed. Fourth doped regions extending from the main surface to the first doped regions are formed. A gate trench having a bottom that is arranged over a portion of one of the first doped regions is formed. A high-temperature step is applied to the substrate so as to realign silicon-carbide atoms along sidewalls of the trench and form rounded corners in the gate trench. A surface layer that forms along the sidewalls of the gate trench during the high-temperature step from the substrate is removed.