公开(公告)号：US20200294896A1

公开(公告)日：2020-09-17

申请号：US16351211

申请日：2019-03-12

Applicant: Infineon Technologies AG

Inventor： Arivindran Navaretnasinggam ,  Xavier Arokiasamy ,  Thomas Bemmerl ,  Ke Yan Tean

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00

Abstract: A packaged semiconductor device includes a die paddle, a semiconductor die mounted on the die paddle, a plurality of fused leads extending away from a first side of the die paddle, a discrete lead that extends away from the first side of the die paddle and is physically detached from the plurality of fused leads, a first electrical connection between a first terminal of the semiconductor die and the discrete lead, an encapsulation material that encapsulates the semiconductor die, and a stabilizer bar connected to a first outer edge side of the discrete lead. The first outer edge side of the discrete lead is opposite from a second outer edge side of the discrete lead which faces the plurality of fused leads.

公开(公告)号：US20240087992A1

公开(公告)日：2024-03-14

申请号：US18453475

申请日：2023-08-22

Applicant: Infineon Technologies AG

Inventor： Ke Yan Tean ,  Edmund Sales Cabatbat ,  Kean Ming Koe

IPC: H01L23/495 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/49524 ,  H01L23/49555 ,  H01L23/49575 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06589

Abstract: A chip package is provided. The chip package includes a first chip, a second chip, an electrically conductive structure to which the first chip and the second chip are mounted, at least one contact terminal for electrically contacting the first chip and/or the second chip, and encapsulation material at least partially encapsulating the first chip, the second chip, and the electrically conductive structure. The encapsulation material forms a chip package body from which the at least one contact terminal protrudes. At least a portion of the electrically conductive structure forms a portion of an outer surface of the chip package body.

公开(公告)号：US11876028B2

公开(公告)日：2024-01-16

申请号：US17502082

申请日：2021-10-15

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Chii Shang Hong ,  Teck Sim Lee ,  Bernd Schmoelzer ,  Ke Yan Tean ,  Lee Shuang Wang

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/495 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/3121 ,  H01L21/56 ,  H01L23/49506 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49555 ,  H01L23/49568 ,  H01L23/49838 ,  H01L24/46 ,  H01L24/49 ,  H01L24/83 ,  H01L23/49503 ,  H01L23/49575 ,  H01L2924/181

Abstract: A package is disclosed. In one example, the package includes a first main face for mounting a heat sink and an opposing second main face for being mounted on a mounting base. The package comprises a carrier, an electronic component mounted at the carrier, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier. Electrically insulating material covers electrically conductive material of the carrier at said first main face. The encapsulant comprises at least one step at the first main face.

公开(公告)号：US11652078B2

公开(公告)日：2023-05-16

申请号：US17234964

申请日：2021-04-20

Applicant: Infineon Technologies AG

Inventor： Edmund Sales Cabatbat ,  Thai Kee Gan ,  Kean Ming Koe ,  Ke Yan Tean

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/495 ,  H01L23/14 ,  H01L23/13

CPC classification number: H01L24/40 ,  H01L23/13 ,  H01L23/14 ,  H01L23/3157 ,  H01L23/49548 ,  H01L24/37 ,  H01L25/0655 ,  H01L2224/37005 ,  H01L2224/37012 ,  H01L2224/4023 ,  H01L2924/182 ,  H01L2924/1815 ,  H01L2924/381

Abstract: A semiconductor package includes a die pad, a semiconductor die mounted on the die pad and comprising a first terminal facing away from the die pad and a second terminal facing and electrically connected to the die pad, an interconnect clip electrically connected to the first terminal, an encapsulant body of electrically insulating material that encapsulates the semiconductor die and the interconnect clip, and a first opening in the encapsulant body that exposes a surface of the interconnect clip, the encapsulant body comprises a lower surface, an upper surface opposite from the lower surface, and a first outer edge side extending between the lower surface and the upper surface, and the first opening is laterally offset from the first outer edge side.

公开(公告)号：US11621204B2

公开(公告)日：2023-04-04

申请号：US17177703

申请日：2021-02-17

Applicant: Infineon Technologies AG

Inventor： Oliver Markus Kreiter ,  Ludwig Busch ,  Angel Enverga ,  Mei Fen Hiew ,  Tian See Hoe ,  Elvis Keli ,  Kean Ming Koe ,  Sanjay Kumar Murugan ,  Michael Niendorf ,  Ivan Nikitin ,  Bernhard Stiller ,  Thomas Stoek ,  Ke Yan Tean

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

Abstract: A semiconductor module includes: a dual-gauge leadframe having thicker and thinner parts, part of the thinner part forming a high voltage lead; a semiconductor die attached to the thicker part; and a molding compound (MC) encapsulating the die. The thicker leadframe part is disposed at a bottom side of the MC. A side face of the MC has a stepped region between the high voltage lead and thicker leadframe part. A first generally vertical part of the stepped region extends from the high voltage lead to the generally horizontal part, a generally horizontal part of the stepped region extends to the second generally vertical part, and a second generally vertical part of the stepped region extends to the bottom side of the MC. A linear dimension of the generally horizontal part as measured from the first generally vertical part to the second generally vertical part is at least 4.5 mm.

公开(公告)号：US20200373228A1

公开(公告)日：2020-11-26

申请号：US16422163

申请日：2019-05-24

Applicant: Infineon Technologies AG

Inventor： Ke Yan Tean ,  Thomas Bemmerl ,  Thai Kee Gan ,  Azlina Kassim

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48

Abstract: A semiconductor package includes a die pad having a die attach surface, a rear surface opposite the die attach surface, and an outer edge side extending between the die attach surface and the rear surface, the outer edge side having a step-shaped profile, wherein an upper section of the die pad laterally overhangs past a lower section of the die pad, a semiconductor die mounted on the die attach surface and having a first electrical terminal on an upper surface of the semiconductor die, and a first conductive clip that directly electrically contacts the first electrical terminal and wraps around the outer edge side of the die pad such that a section of the first conductive clip is at least partially within an area that is directly below the upper section of the die pad and directly laterally adjacent to the lower section.