公开(公告)号：US20240312956A1

公开(公告)日：2024-09-19

申请号：US18122776

申请日：2023-03-17

Applicant: Infineon Technologies AG

Inventor： Pei Luan Pok ,  Swee Kah Lee ,  Soon Lock Goh ,  Chee Hong Lee ,  Samsun Paing ,  Chee Chiew Chong

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L24/96 ,  H01L21/4821 ,  H01L21/561 ,  H01L21/568 ,  H01L24/11 ,  H01L2224/11 ,  H01L2224/96

Abstract: A method of forming a semiconductor package includes providing a baseplate, mounting a semiconductor die on the baseplate with a main surface of the semiconductor die facing away from the baseplate, forming vertical interconnect elements on the main surface of the semiconductor die, forming an encapsulant on the baseplate that encapsulates the semiconductor die, exposing the vertical interconnect elements at an upper surface of the encapsulant, forming a first level metal pad on the upper surface of the encapsulant that contacts the exposed vertical interconnect elements, and forming structured metal regions on the upper surface of the encapsulant, wherein forming the structured metal regions includes structuring the first level metal pad.

公开(公告)号：US10396007B2

公开(公告)日：2019-08-27

申请号：US15448018

申请日：2017-03-02

Applicant: Infineon Technologies AG

Inventor： Sook Woon Chan ,  Chau Fatt Chiang ,  Kok Yau Chua ,  Soon Lock Goh ,  Swee Kah Lee ,  Joachim Mahler ,  Mei Chin Ng ,  Beng Keh See ,  Guan Choon Matthew Nelson Tee

IPC: H01L23/552 ,  H01L23/31 ,  C09D5/00 ,  C09D201/00 ,  C23C18/16 ,  C23C18/18 ,  C23C18/34 ,  H01L21/56 ,  H01L23/29 ,  H01L23/66 ,  H01L23/00 ,  C09D5/24

Abstract: A package which comprises a first encapsulant configured so that electrically conductive material is plateable thereon, and a second encapsulant configured so that electrically conductive material is not plateable thereon.

公开(公告)号：US20190027430A1

公开(公告)日：2019-01-24

申请号：US16036127

申请日：2018-07-16

Applicant: Infineon Technologies AG

Inventor： Soon Lock Goh

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/02

Abstract: A semiconductor package and method for fabricating a semiconductor package is disclosed. In one aspect, the method includes providing a substrate, at least partially encapsulating the substrate in an encapsulation body, and depositing by electroplating a first Ni layer on a first surface of the substrate. A second Ni layer by electroless Ni plating is deposited on the first Ni layer.

公开(公告)号：US09852918B2

公开(公告)日：2017-12-26

申请号：US14835750

申请日：2015-08-26

Applicant: Infineon Technologies AG

Inventor： Peh Hean Teh ,  Jagen Krishnan ,  Swee Kah Lee ,  Poh Cheng Lim ,  Joachim Mahler ,  Chew Theng Tai ,  Yik Yee Tan ,  Soon Lock Goh

IPC: H01L23/29 ,  H01L21/3105 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  C09J163/00

CPC classification number: H01L21/3105 ,  C09J163/00 ,  H01L21/56 ,  H01L23/295 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/49513 ,  H01L23/49548 ,  H01L23/49555 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/8392 ,  H01L2224/8592 ,  H01L2224/92247 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An electronic device comprising a carrier having a mounting surface, at least one electronic chip mounted on the mounting surface, an encapsulant at least partially encapsulating the carrier and the at least one electronic chip, and a plurality of capsules in the encapsulant, wherein the capsules comprise a core comprising an additive and comprise a shell, in particular a crackable shell, enclosing the core.