公开(公告)号：US10396007B2

公开(公告)日：2019-08-27

申请号：US15448018

申请日：2017-03-02

Applicant: Infineon Technologies AG

Inventor： Sook Woon Chan ,  Chau Fatt Chiang ,  Kok Yau Chua ,  Soon Lock Goh ,  Swee Kah Lee ,  Joachim Mahler ,  Mei Chin Ng ,  Beng Keh See ,  Guan Choon Matthew Nelson Tee

IPC: H01L23/552 ,  H01L23/31 ,  C09D5/00 ,  C09D201/00 ,  C23C18/16 ,  C23C18/18 ,  C23C18/34 ,  H01L21/56 ,  H01L23/29 ,  H01L23/66 ,  H01L23/00 ,  C09D5/24

Abstract: A package which comprises a first encapsulant configured so that electrically conductive material is plateable thereon, and a second encapsulant configured so that electrically conductive material is not plateable thereon.

公开(公告)号：US11081417B2

公开(公告)日：2021-08-03

申请号：US16514853

申请日：2019-07-17

Applicant: Infineon Technologies AG

Inventor： Sook Woon Chan ,  Chau Fatt Chiang ,  Kok Yau Chua ,  Soon Lock Goh ,  Swee Kah Lee ,  Joachim Mahler ,  Mei Chin Ng ,  Beng Keh See ,  Guan Choon Matthew Nelson Tee

IPC: H01L23/552 ,  H01L23/31 ,  C09D5/24 ,  C23C18/16 ,  C23C18/18 ,  H01L23/29 ,  C09D5/00 ,  C09D201/00 ,  C23C18/34 ,  H01L21/56 ,  H01L23/66 ,  H01L23/00

Abstract: A method of manufacturing a package, comprising embedding the semiconductor chip with an encapsulant comprising a transition metal in a concentration in a range between 10 ppm and 10,000 ppm; selectively converting of a part of the transition metal, such that the electrical conductivity of the encapsulant increases; and plating the converted part of the encapsulant with an electrically conductive material.

公开(公告)号：US10549985B2

公开(公告)日：2020-02-04

申请号：US15692938

申请日：2017-08-31

Applicant: Infineon Technologies AG

Inventor： Dominic Maier ,  Matthias Steiert ,  Chau Fatt Chiang ,  Christian Geissler ,  Bernd Goller ,  Thomas Kilger ,  Johannes Lodermeyer ,  Franz-Xaver Muehlbauer ,  Chee Yang Ng ,  Beng Keh See ,  Claus Waechter

IPC: B81B7/00 ,  B81C1/00

Abstract: A semiconductor package includes a semiconductor die having a sensor structure disposed at a first side of the semiconductor die, and a first port extending through the semiconductor die from the first side to a second side of the semiconductor die opposite the first side, so as to provide a link to the outside environment. Corresponding methods of manufacture are also provided.

公开(公告)号：US20140231971A1

公开(公告)日：2014-08-21

申请号：US13771222

申请日：2013-02-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Horst Theuss ,  Beng Keh See

IPC: H01L23/552 ,  H01L21/56

CPC classification number: H01L23/552 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L24/85 ,  H01L2924/00 ,  H01L2224/85 ,  H01L2924/00012

Abstract: In various embodiments, a chip arrangement may be provided. The chip arrangement may include a metallic carrier. The chip arrangement may also include at least one chip arranged on the metallic carrier, wherein the at least one chip includes a chip contact, wherein the chip contact is electrically coupled to the metallic carrier. The chip arrangement may also include encapsulation material at least partially encapsulating the at least one chip. The chip arrangement may also include an electrically conductive shielding structure formed over at least a portion of the encapsulation material to electrically contact the metallic carrier.

Abstract translation: 在各种实施例中，可以提供芯片布置。 芯片布置可以包括金属载体。 芯片布置还可以包括布置在金属载体上的至少一个芯片，其中至少一个芯片包括芯片触点，其中芯片触点电耦合到金属载体。 芯片布置还可以包括至少部分地封装至少一个芯片的封装材料。 芯片布置还可以包括形成在封装材料的至少一部分上以与金属载体电接触的导电屏蔽结构。

公开(公告)号：US20180148322A1

公开(公告)日：2018-05-31

申请号：US15692938

申请日：2017-08-31

Applicant: Infineon Technologies AG

Inventor： Dominic Maier ,  Matthias Steiert ,  Chau Fatt Chiang ,  Christian Geissler ,  Bernd Goller ,  Thomas Kilger ,  Johannes Lodermeyer ,  Franz-Xaver Muehlbauer ,  Chee Yang Ng ,  Beng Keh See ,  Claus Waechter

IPC: B81B7/00 ,  B81C1/00

Abstract: A semiconductor package includes a semiconductor die having a sensor structure disposed at a first side of the semiconductor die, and a first port extending through the semiconductor die from the first side to a second side of the semiconductor die opposite the first side, so as to provide a link to the outside environment. Corresponding methods of manufacture are also provided.

公开(公告)号：US09653405B2

公开(公告)日：2017-05-16

申请号：US13771222

申请日：2013-02-20

Applicant: Infineon Technologies AG

Inventor： Horst Theuss ,  Beng Keh See

IPC: H01L23/552 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/552 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L24/85 ,  H01L2924/00 ,  H01L2224/85 ,  H01L2924/00012

Abstract: In various embodiments, a chip arrangement may be provided. The chip arrangement may include a metallic carrier. The chip arrangement may also include at least one chip arranged on the metallic carrier, wherein the at least one chip includes a chip contact, wherein the chip contact is electrically coupled to the metallic carrier. The chip arrangement may also include encapsulation material at least partially encapsulating the at least one chip. The chip arrangement may also include an electrically conductive shielding structure formed over at least a portion of the encapsulation material to electrically contact the metallic carrier.