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公开(公告)号：US11176994B2
公开(公告)日：2021-11-16
申请号：US17001432
申请日：2020-08-24
申请人： Intel Corporation
IPC分类号： G11C11/00 , G11C13/00 , G11C11/419 , G11C11/412 , G11C7/12 , G11C7/10 , G11C11/418 , G11C7/22
摘要： Embodiments include apparatuses, methods, and systems to implement a multi-read and/or multi-write process with a set of memory cells. The set of memory cells may be multiplexed with a same sense amplifier. As part of a multi-read process, a memory controller coupled to a memory circuit may precharge the bit lines associated with the set of memory cells, provide a single assertion of a word line signal on the word line, and then sequentially read data from the set of memory cells (using the sense amplifier) based on the precharge and the single assertion of the word line signal. Additionally, or alternatively, a multi-write process may be performed to sequentially write data to the set of memory cells based on one precharge of the associated bit lines. Other embodiments may be described and claimed.
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公开(公告)号：US20210240142A1
公开(公告)日：2021-08-05
申请号：US17125768
申请日：2020-12-17
申请人： Intel Corporation
发明人： Suyoung Bang , Wootaek Lim , Eric Samson , Charles Augustine , Muhammad Khellah
摘要： A distributed and scalable all-digital LDO (D-DLDO) voltage regulator allowing rapid scaling across technology nodes. The distributed DLDO includes many tillable DLDO units regulating a single supply voltage with a shared power distribution network (PDN). The D-DLDO includes an all-digital proportional-integral-derivative (PID) controller that receives a first code indicative of a voltage behavior on a power supply rail. A droop detector is provided to compare the first code with a threshold to determine a droop event, wherein information about the droop event is provided to the PID controller, wherein the PID controller generates a second code according to the first code and the information about the droop event. The DLDO includes a plurality of power gates that receive the second code.
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公开(公告)号：US10784874B1
公开(公告)日：2020-09-22
申请号：US16783096
申请日：2020-02-05
申请人： Intel Corporation
发明人： Suyoung Bang , Eric Samson , Wootaek Lim , Charles Augustine , Muhammad Khellah
摘要： An all-digital voltage monitor (ADVM) generates a multi-bit output code that changes in proportion to a voltage being monitored, by leveraging the voltage impact on a gate delay. ADVM utilizes a simple delay chain, which receives a clock-cycle-long pulse every clock cycle, such that the monitored supply voltage is sampled for one full cycle every cycle. The outputs of all delay cells of the delay chain collectively represents a current voltage state as a digital thermometer code. In AVDM, a voltage droop event thus results in a decrease in the output code from a nominal value, while an overshoot results in an increase in the output code.
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公开(公告)号：US10748060B2
公开(公告)日：2020-08-18
申请号：US15294666
申请日：2016-10-14
申请人： Intel Corporation
摘要： A processor or integrated circuit includes a memory to store weight values for a plurality neuromorphic states and a circuitry coupled to the memory. The circuitry is to detect an incoming data signal for a pre-synaptic neuromorphic state and initiate a time window for the pre-synaptic neuromorphic state in response to detecting the incoming data signal. The circuitry is further to, responsive to detecting an end of the time window: retrieve, from the memory, a weight value for a post-synaptic neuromorphic state for which an outgoing data signal is generated during the time window, the post-synaptic neuromorphic state being a fan-out connection of the pre-synaptic neuromorphic state; perform a causal update to the weight value, according to a learning function, to generate an updated weight value; and store the updated weight value back to the memory.
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公开(公告)号：US10297302B2
公开(公告)日：2019-05-21
申请号：US15371122
申请日：2016-12-06
申请人： Intel Corporation
发明人： Charles Augustine , Shigeki Tomishima , Wei Wu , Shih-Lien Lu , James W. Tschanz , Georgios Panagopoulos , Helia Naeimi
IPC分类号： G11C11/16
摘要： An apparatus is described that includes a semiconductor chip memory array having resistive storage cells. The apparatus also includes a comparator to compare a first word to be written into the array against a second word stored in the array at the location targeted by a write operation that will write the first word into the array. The apparatus also includes circuitry to iteratively write to one or more bit locations where a difference exists between the first word and the second word with increasing write current intensity with each successive iteration.
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公开(公告)号：US20180322384A1
公开(公告)日：2018-11-08
申请号：US15584510
申请日：2017-05-02
申请人： Intel Corporation
摘要： A spike sent from a first artificial neuron in a spiking neural network (SNN) to a second artificial neuron in the SNN is identified, with the spike sent over a particular artificial synapse in the SNN. The membrane potential of the second artificial neuron at a particular time step, corresponding to sending of the spike, is compared to a threshold potential, where the threshold potential is set lower than a firing potential of the second artificial neuron. A change to the synaptic weight of the particular artificial synapse is determined based on the spike, where the synaptic weight is to be decreased if the membrane potential of the second artificial neuron is lower than the threshold potential at the particular time step and the synaptic weight is to be increased if the membrane potential of the second artificial neuron is higher than the threshold potential at the particular time step.
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17.发明授权公开(公告)号：US09734880B1
公开(公告)日：2017-08-15
申请号：US15088419
申请日：2016-04-01
申请人： Intel Corporation
CPC分类号： G11C11/161 , G06N3/049 , G06N3/0635 , G06N3/088 , G06N5/025 , G11C11/1653 , G11C11/1657 , G11C11/1659 , G11C11/1675 , G11C11/54 , G11C13/0002
摘要： Embodiments include apparatuses, systems, and methods including a memory apparatus including a plurality of bit cells, wherein each of the plurality of bit cells correspond to a respective weight value and include a switch device that has a magnetic tunnel junction (MTJ) or other suitable resistive memory element to produce stochastic switching. In embodiments, the switch device may produce a switching output according to a stochastic switching probability of the switch device. In embodiments, a bit line or a source line passes a current across the MTJ for a switching time associated with the stochastic switching probability to produce the switching output which enables a determination of whether the respective weight value is to be updated. Other embodiments may also be described and claimed.
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公开(公告)号：US20170041001A1
公开(公告)日：2017-02-09
申请号：US15331280
申请日：2016-10-21
申请人： INTEL CORPORATION
CPC分类号： H03K19/0016 , G05F1/10 , G05F1/461 , G05F1/59 , G06F1/3287 , G06F1/3296 , H03K3/0377 , H03K19/0008
摘要： Described is an apparatus which comprises: a clamp coupled between a first power supply and a second power supply, the clamp including a plurality of transistors, a circuit to operate with the second power supply; and a control unit to turn on and off the plurality of transistors to adjust the second power supply when the apparatus enters a low power mode. The control unit includes a first comparator to compare the second power supply with a first reference, a second comparator to compare the second power supply with a second reference, and a counter. The counter counts up when the second power supply is higher than the first reference and counts down when the second power supply is lower than the second reference.
摘要翻译： 描述了一种装置，其包括：夹紧器，其耦合在第一电源和第二电源之间，所述夹具包括多个晶体管，用于与所述第二电源一起操作的电路; 以及控制单元，用于在所述设备进入低功率模式时接通和断开所述多个晶体管以调节所述第二电源。 控制单元包括用于将第二电源与第一参考值进行比较的第一比较器，将第二电源与第二参考电压进行比较的第二比较器和计数器。 当第二电源高于第一个参考电压时，计数器递增计数，当第二个电源低于第二个参考电压时，计数器递减计数。
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公开(公告)号：US09299412B2
公开(公告)日：2016-03-29
申请号：US14191191
申请日：2014-02-26
申请人： Intel Corporation
发明人： Helia Naeimi , Shih-Lien L. Lu , Charles Augustine
CPC分类号： G11C11/1675 , G11C7/1009 , G11C11/1657
摘要： In one embodiment, a controller comprises logic to identify a first plurality of cells in a row of spin transfer torque (STT) memory which are to be set to a parallel state and a second plurality of cells in the row of the STT memory which are to be set to an anti-parallel state, mask write operations to the second plurality of cells in the row, set the first plurality of cells to a parallel state, mask write operations to the first plurality of cells in the row, and set the second plurality of cells to an anti-parallel state.
摘要翻译： 在一个实施例中，控制器包括用于识别要被设置为并行状态的一行自旋转移转矩（STT）存储器中的第一个多个单元的逻辑，以及STT存储器的行中的第二多个单元 被设置为反并行状态，对行中的第二多个单元进行掩模写入操作，将第一多个单元设置为并行状态，对该行中的第一多个单元进行掩码写入操作，并将 第二多个单元格到反并行状态。
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公开(公告)号：US20150243335A1
公开(公告)日：2015-08-27
申请号：US14191191
申请日：2014-02-26
申请人： Intel Corporation
发明人： Helia Naeimi , Shih-Lien L. Lu , Charles Augustine
IPC分类号： G11C11/16
CPC分类号： G11C11/1675 , G11C7/1009 , G11C11/1657
摘要： In one embodiment, a controller comprises logic to identify a first plurality of cells in a row of spin transfer torque (STT) memory which are to be set to a parallel state and a second plurality of cells in the row of the STT memory which are to be set to an anti-parallel state, mask write operations to the second plurality of cells in the row, set the first plurality of cells to a parallel state, mask write operations to the first plurality of cells in the row, and set the second plurality of cells to an anti-parallel state.
摘要翻译： 在一个实施例中，控制器包括用于识别要被设置为并行状态的一行自旋转移转矩（STT）存储器中的第一个多个单元的逻辑，以及STT存储器的行中的第二多个单元 被设置为反并行状态，对行中的第二多个单元进行掩模写入操作，将第一多个单元设置为并行状态，对该行中的第一多个单元进行掩码写入操作，并将 第二多个单元格到反并行状态。
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