公开(公告)号：US20030061591A1

公开(公告)日：2003-03-27

申请号：US10281752

申请日：2002-10-28

Applicant: Intel Corporation

Inventor： Yuan-Liang Li ,  David G. Figueroa

IPC: G06F017/50 ,  H03K017/693

CPC classification number: H01F17/0033 ,  H01F41/041 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15312 ,  H05K1/115 ,  H05K1/165 ,  H05K3/06 ,  H05K3/42 ,  H05K2201/086 ,  H05K2201/097 ,  H05K2201/1006 ,  H05K2203/0723 ,  H01L2224/0401

Abstract: A series of plated through hole (PTH) vias are interconnected by traces that alternate between a top surface and a bottom surface of a dielectric board. The PTH vias in the series can be positioned to create a collinear inductive filter, a coil-type inductive filter, or a transformer. Multiple, electrically isolated series of interconnected PTH vias can be used as a multi-phase inductive filter in one embodiment. In another embodiment, multiple series of interconnected PTH vias are electrically connected by a linking portion of conductive material, resulting in a low-resistance inductive filter. Ferromagnetic material patterns can be embedded in the dielectric board to enhance the inductive characteristics of the interconnected via structures. In one embodiment, a closed-end pattern is provided with two series of interconnected vias coiling around the pattern, resulting in an embedded transformer structure. A method of producing an interconnected series of PTH vias includes providing a dielectric board having a series of holes. In some embodiments, the board includes an embedded ferromagnetic material pattern. The holes and the top and bottom surface of the dielectric board have a conductive material thereupon. Portions of the conductive material are selectively removed, resulting in the embedded inductive filter and/or transformer structure.

公开(公告)号：US20020134581A1

公开(公告)日：2002-09-26

申请号：US10155628

申请日：2002-05-24

Applicant: Intel Corporation

Inventor： David G. Figueroa ,  Yuan-Liang Li ,  Huong T. Do

IPC: H05K001/16 ,  H01G004/38 ,  H01L029/00

CPC classification number: H01L23/642 ,  H01L2924/0002 ,  H01L2924/15312 ,  H01L2924/19105 ,  H05K1/141 ,  H05K1/162 ,  Y10T29/435 ,  H01L2924/00

Abstract: A hybrid capacitor associated with an integrated circuit package provides multiple levels of excess, off-chip capacitance to die loads. The hybrid capacitor includes a low inductance, parallel plate capacitor embedded within the package, and electrically connected to a second source of off-chip capacitance. The parallel plate capacitor is disposed underneath a die, and includes a top conductive layer, a bottom conductive layer, and a thin dielectric layer that electrically isolates the top and bottom layers. The second source of off-chip capacitance is a set of self-aligned via capacitors, and/or one or more discrete capacitors, and/or an additional parallel plate capacitor. Each of the self-aligned via capacitors is embedded within the package, and has an inner conductor and an outer conductor. The inner conductor is electrically connected to either the top or bottom conductive layer, and the outer conductor is electrically connected to the other conductive layer. The discrete capacitors are electrically connected to contacts from the conductive layers to the surface of the package. During operation, one of the conductive layers of the low inductance parallel plate capacitor provides a ground plane, while the other conductive layer provides a power plane.

Abstract translation: 与集成电路封装相关联的混合电容为裸片负载提供多级多余的片外电容。 混合电容器包括嵌入在封装内的低电感并联板电容器，并且电连接到片外电容的第二源极。 平行板电容器设置在管芯下方，并且包括顶部导电层，底部导电层和电绝缘顶层和底层的薄介电层。 片外电容的第二个源是一组自对准通孔电容器和/或一个或多个分立电容器和/或附加的平行板电容器。 每个自对准通孔电容器嵌入在封装内，并具有内部导体和外部导体。 内部导体电连接到顶部或底部导电层，并且外部导体电连接到另一个导电层。 分立电容器电连接到从导电层到封装表面的触点。 在操作期间，低电感平行板电容器的导电层之一提供接地平面，而另一导电层提供电源平面。

公开(公告)号：US20020085334A1

公开(公告)日：2002-07-04

申请号：US09751612

申请日：2000-12-29

Applicant: Intel Corporation

Inventor： David G. Figueroa ,  Kishore K. Chakravorty ,  Huong T. Do ,  Larry Eugene Mosley ,  Jorge Pedro Rodriguez ,  Ken Brown

IPC: H01G004/30

CPC classification number: H01G4/30 ,  H01L23/642 ,  H01L2224/16225 ,  H01L2924/00014 ,  H05K1/0298 ,  H05K1/162 ,  H01L2224/0401

Abstract: A capacitor includes multiple tiers (302, 304, 306, 1210, 1212, 1310, 1312, 1380, FIGS. 3, 12, 13), which provide capacitance to a load at different inductance values. Each tier includes multiple layers (311-325, 1220, 1222, 1320, 1322, 1382, FIGS. 3, 12, 13) of patterned conductive material, which are separated by layers of dielectric material. In one embodiment, tiers are stacked in a vertical direction, and are electrically connected through vias (330, 332, 334, 1230, 1232, FIGS. 3, 12) that extend through some or all of the tiers. In another embodiment, one or more tiers (1310, 1312, FIG. 13) are located in a center region (1404, FIG. 14) of the capacitor, and one or more other tiers (1380, FIG. 13) are located in a peripheral region (1408, FIG. 14) of the capacitor. In that embodiment, the center tiers and peripheral tiers are electrically connected through one or more additional layers (1370, FIG. 13) of patterned conductive material. The capacitors of the various embodiments can be used as discrete devices, which are mountable on or embeddable within a housing (e.g., a package, interposer, socket or PC board), or they can be integrally fabricated within the housing.

Abstract translation: 电容器包括多层（302,304,306,1210,1212,1310,1312,1380，图3,12,13），其以不同的电感值向负载提供电容。 每个层包括被介电材料层隔开的图案化导电材料的多层（311-325,1220,1222,1320,1322,1382，图3,12,13）。 在一个实施例中，层是沿垂直方向堆叠的，并且通过延伸穿过一些或所有层的通孔（330,332,334,1230,1232，图3,12）电连接。 在另一个实施例中，一个或多个层（1310,1312，图13）位于电容器的中心区域（1404，图14）中，并且一个或多个其他层（图13中的1380）位于 电容器的外围区域（1408，图14）。 在该实施例中，中心层和外围层通过图案化导电材料的一个或多个附加层（1370，图13）电连接。 各种实施例的电容器可以用作可安装在壳体（例如，封装，插入件，插座或PC板）中或嵌入其中的分立器件，或者它们可以一体地制造在壳体内。

公开(公告)号：US20040022038A1

公开(公告)日：2004-02-05

申请号：US10210391

申请日：2002-07-31

Applicant: Intel Corporation

Inventor： David G. Figueroa ,  Chris Baldwin ,  Yuan-Liang Li

IPC: H05K007/06 ,  H01L023/58

CPC classification number: H01L23/642 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15312 ,  H01L2924/19106 ,  H01L2924/30107 ,  H05K1/0231 ,  H05K1/183 ,  H01L2924/00 ,  H01L2224/0401

Abstract: An electronic package, such as an integrated circuit package, includes a cavity (310, 410 FIGS. 3, 4) on the back side of the package, which is the same side on which connectors (304, 408, FIGS. 3, 4) to a next level of interconnect are located. Within the cavity are contacts (312, 412, FIGS. 3, 4), which enable one or more discrete capacitors (302, 402, FIGS. 3, 4) to be electrically connected to the package. The package provides a very low vertical inductance path between the capacitors and an integrated circuit (314, FIG. 3) mounted on the front side of the package.

Abstract translation: 诸如集成电路封装的电子封装包括在封装的背面上的空腔（310,410，图3,4），其是连接器（304,408，图3，图4）上相同的一侧 ）到下一级互连。 在腔内是使得一个或多个分立电容器（302,402，图3，图4）能够电连接到封装件的触头（312,412，图3，图4）。 该封装在电容器和安装在封装的前侧上的集成电路（314，图3）之间提供非常低的垂直电感路径。

公开(公告)号：US20030151147A1

公开(公告)日：2003-08-14

申请号：US10371827

申请日：2003-02-21

Applicant: Intel Corporation

Inventor： Chee-Yee Chung ,  David G. Figueroa ,  Robert L. Sankman

IPC: H01L023/48

CPC classification number: H05K1/141 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K1/0231 ,  H05K1/0298 ,  H05K3/3436 ,  H05K3/366 ,  H05K2201/0919 ,  H05K2201/10446 ,  H05K2201/10454 ,  H05K2201/10674 ,  H05K2201/10719 ,  H01L2224/05599

Abstract: An electronic circuit package includes a vertical package section (304, FIG. 3) electrically connected to a horizontal package section (306, FIG. 3). The vertical package section includes multiple conductive layers (512, 514, 516, FIG. 5) oriented in parallel with a vertical plane. A first set of bond pads (606, FIG. 6) on the vertical section's horizontal top surface (608, FIG. 6) can be connected to the bond pads (602, FIG. 6) of an integrated circuit (302, FIG. 3). A second set of bond pads (612, FIG. 6) on the vertical section's horizontal bottom surface (614, FIG. 6) can be connected to bond pads (616, FIG. 6) on the horizontal package section. The conductive layers of the vertical section perform a bond pad pitch conversion in a first direction, and conductive structures (906, 908, 910, FIG. 9) within the horizontal package section perform a bond pad pitch conversion in a second direction.

Abstract translation: 电子电路封装包括电连接到水平封装部分（图3的306）的垂直封装部分（304，图3）。 垂直封装部分包括与垂直平面平行取向的多个导电层（512,514,516，图5）。 垂直部分的水平顶面（图6中的608）上的第一组接合焊盘（606，图6）可以连接到集成电路（图6的302）的接合焊盘（602，图6）。 3）。 垂直部分的水平底面（图6中的614）上的第二组接合焊盘（612，图6））可以连接到水平封装部分上的接合焊盘（616，图6）。 垂直部分的导电层在第一方向上进行接合焊盘间距转换，并且水平封装部分内的导电结构（906,908,910，图9）在第二方向上执行接合焊盘间距转换。

公开(公告)号：US20030003705A1

公开(公告)日：2003-01-02

申请号：US09897369

申请日：2001-07-02

Applicant: Intel Corporation

Inventor： Chee-Yee Chung ,  David G. Figueroa ,  Robert L. Sankman

IPC: H01L021/44

CPC classification number: H05K1/141 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K1/0231 ,  H05K1/0298 ,  H05K3/3436 ,  H05K3/366 ,  H05K2201/0919 ,  H05K2201/10446 ,  H05K2201/10454 ,  H05K2201/10674 ,  H05K2201/10719 ,  H01L2224/05599

Abstract: An electronic circuit package includes a vertical package section (304, FIG. 3) electrically connected to a horizontal package section (306, FIG. 3). The vertical package section includes multiple conductive layers (512, 514, 516, FIG. 5) oriented in parallel with a vertical plane. A first set of bond pads (606, FIG. 6) on the vertical section's horizontal top surface (608, FIG. 6) can be connected to the bond pads (602, FIG. 6) of an integrated circuit (302, FIG. 3). A second set of bond pads (612, FIG. 6) on the vertical section's horizontal bottom surface (614, FIG. 6) can be connected to bond pads (616, FIG. 6) on the horizontal package section. The conductive layers of the vertical section perform a bond pad pitch conversion in a first direction, and conductive structures (906, 908, 910, FIG. 9) within the horizontal package section perform a bond pad pitch conversion in a second direction.

Abstract translation: 电子电路封装包括电连接到水平封装部分（图3的306）的垂直封装部分（304，图3）。 垂直封装部分包括与垂直平面平行取向的多个导电层（512,514,516，图5）。 垂直部分的水平顶面（图6中的608）上的第一组接合焊盘（606，图6）可以连接到集成电路（图6的302）的接合焊盘（602，图6）。 3）。 垂直部分的水平底面（图6中的614）上的第二组接合焊盘（612，图6））可以连接到水平封装部分上的接合焊盘（616，图6）。 垂直部分的导电层在第一方向上进行接合焊盘间距转换，并且水平封装部分内的导电结构（906,908,910，图9）在第二方向上执行接合焊盘间距转换。