公开(公告)号：US11705377B2

公开(公告)日：2023-07-18

申请号：US17720202

申请日：2022-04-13

Applicant: Intel Corporation

Inventor： Mitul Modi ,  Robert L. Sankman ,  Debendra Mallik ,  Ravindranath V. Mahajan ,  Amruthavalli P. Alur ,  Yikang Deng ,  Eric J. Li

IPC: H01L23/13 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L23/13 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L21/4853 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06586 ,  H01L2924/1432 ,  H01L2924/1434

Abstract: An apparatus is provided which comprises: a plurality of dielectric layers forming a substrate, a plurality of first conductive contacts on a first surface of the substrate, a cavity in the first surface of the substrate defining a second surface parallel to the first surface, a plurality of second conductive contacts on the second surface of the substrate, one or more integrated circuit die(s) coupled with the second conductive contacts, and mold material at least partially covering the one or more integrated circuit die(s) and the first conductive contacts. Other embodiments are also disclosed and claimed.

公开(公告)号：US20190355666A1

公开(公告)日：2019-11-21

申请号：US16510295

申请日：2019-07-12

Applicant: Intel Corporation

Inventor： Eric J. Li ,  Timothy A. Gosselin ,  Yoshihiro Tomita ,  Shawna M. Liff ,  Amram Eitan ,  Mark Saltas

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L23/13 ,  H01L21/56 ,  H01L23/48 ,  H01L25/065

Abstract: A microelectronic structure includes a microelectronic substrate having a first surface and a cavity extending into the substrate from the microelectronic substrate first surface, a first microelectronic device and a second microelectronic device attached to the microelectronic substrate first surface, and a microelectronic bridge disposed within the microelectronic substrate cavity and attached to the first microelectronic device and to the second microelectronic device. In one embodiment, the microelectronic structure may include a reconstituted wafer formed from the first microelectronic device and the second microelectronic device. In another embodiment, a flux material may extend between the first microelectronic device and the microelectronic bridge and between the second microelectronic device and the microelectronic bridge.

公开(公告)号：US10121722B1

公开(公告)日：2018-11-06

申请号：US15721880

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Chandra M. Jha ,  Eric J. Li ,  Zhaozhi Li ,  Robert M. Nickerson

IPC: H01L23/34 ,  H01L23/373 ,  H01L23/00

Abstract: A device package and a method of forming the device package are described. The device package has a package layer disposed on a substrate. The package layer includes a mold layer surrounding solder balls and a die. The device package also has a trench disposed in the mold layer to surround the die of the package layer. The device package further includes a conductive layer disposed on a top surface of the die. The conductive layer is disposed over the top surface of the die and in the trench of the package layer. The trench may have a specified distance between the die edges, and a specified width and a specified depth based on the conductive layer. The device package may include an interposer with solder balls disposed on the conductive layer and above the package layer, and an underfill layer disposed between the interposer and the package layer.

公开(公告)号：US09922751B2

公开(公告)日：2018-03-20

申请号：US15088924

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Zhichao Zhang ,  Gong Ouyang ,  Kai Xiao ,  Eric J. Li ,  Kemal Aygun

IPC: H01B7/00 ,  H01B7/02 ,  H05K9/00 ,  H01B13/08 ,  H01B13/22

CPC classification number: H01B7/0241 ,  H01B11/1856 ,  H01B11/20 ,  H01B13/08 ,  H01B13/22 ,  H05K9/0098

Abstract: A helically wound insulated twinax cable reduces cable dielectric loss by increasing the percentage of air in the dielectric filler surrounding the signal conductors. The helical insulator wire winding further provides mechanical support and reduces the risk of creating an electrical short-circuit. This will improve differential signaling capability of the two-conductor cable and enable longer cable range.

公开(公告)号：US20170278816A1

公开(公告)日：2017-09-28

申请号：US15083089

申请日：2016-03-28

Applicant: Intel Corporation

Inventor： Eric J. Li ,  Jimin Yao ,  Shawna M. Liff

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L21/4853 ,  H01L23/49816 ,  H01L24/11 ,  H01L2224/11003 ,  H01L2224/1403 ,  H01L2224/14132 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/0133

Abstract: BGA packages with a spatially varied ball height, molds and techniques to form such packages. A template or mold with cavities may be pre-fabricated to hold solder paste material applied to the mold, for example with a solder paste printing process. The depth and/or diameter of the cavities may be predetermined as a function of spatial position within the mold working surface area. Mold cavity dimensions may be specified corresponding to package position to account for one or more pre-existing or expected spatial variations in the package, such as a package-level warpage measurement. Any number of different ball heights may be provided. The molds may be employed in a standardize process that need not be modified with each change in the mold.

公开(公告)号：US20170271270A1

公开(公告)日：2017-09-21

申请号：US15074050

申请日：2016-03-18

Applicant: Intel Corporation

Inventor： Rajendra C. Dias ,  Anna M. Prakash ,  Joshua D. Heppner ,  Eric J. Li ,  Nachiket R. Raravikar

IPC: H01L23/552 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31

CPC classification number: H01L23/552 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include a substrate including electrical connection circuitry therein, grounding circuitry on, or at least partially in the substrate, the grounding circuitry at least partially exposed from a surface of the substrate, a die electrically connected to the connection circuitry and the grounding circuitry, the die on the substrate, and a conductive foil or conductive film surrounding the die, the conductive foil or conductive film electrically connected to the grounding circuitry.

公开(公告)号：US10790231B2

公开(公告)日：2020-09-29

申请号：US16510295

申请日：2019-07-12

Applicant: Intel Corporation

Inventor： Eric J. Li ,  Timothy A. Gosselin ,  Yoshihiro Tomita ,  Shawna M. Liff ,  Amram Eitan ,  Mark Saltas

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/13 ,  H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L23/31

Abstract: A microelectronic structure includes a microelectronic substrate having a first surface and a cavity extending into the substrate from the microelectronic substrate first surface, a first microelectronic device and a second microelectronic device attached to the microelectronic substrate first surface, and a microelectronic bridge disposed within the microelectronic substrate cavity and attached to the first microelectronic device and to the second microelectronic device. In one embodiment, the microelectronic structure may include a reconstituted wafer formed from the first microelectronic device and the second microelectronic device. In another embodiment, a flux material may extend between the first microelectronic device and the microelectronic bridge and between the second microelectronic device and the microelectronic bridge.

公开(公告)号：US10672626B2

公开(公告)日：2020-06-02

申请号：US15469284

申请日：2017-03-24

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Aditya S. Vaidya ,  Nachiket R. Raravikar ,  Eric J. Li

IPC: H01L21/56 ,  H01L21/768 ,  H01L21/78 ,  H01L23/498 ,  H01L25/10 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31

Abstract: Embodiments describe a semiconductor package that includes a substrate, a die bonded to the substrate, and a solder paste overmold layer formed over a top surface of the die. In an embodiment, the solder paste comprises a high-melting point metal, a solder matrix, intermetallic compounds and a polymer. The overmold layer has a high elastic modulus, a coefficient of thermal expansion similar to the substrate, and reduces the warpage of the package. In an embodiment, interconnects of a semiconductor package are formed with a no-slump solder paste that includes vents. Vents may be formed through a conductive network formed by the high-melting point metal, solder matrix and intermetallic compounds. In an embodiment, vents provide a path through the interconnect that allows for moisture outgassing. In an embodiment, a mold layer may be mechanically anchored to the interconnects by the vents, thereby providing improved mechanical continuity to the mold layer.

公开(公告)号：US10573608B2

公开(公告)日：2020-02-25

申请号：US15776021

申请日：2015-12-22

Applicant: INTEL CORPORATION

Inventor： Georgios C. Dogiamis ,  Telesphor Kamgaing ,  Eric J. Li ,  Javier A. Falcon ,  Yoshihiro Tomita ,  Vijay K. Nair ,  Shawna M. Liff

IPC: H01L23/66 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552 ,  H01L25/16

Abstract: Embodiments of the invention include a microelectronic device that includes a first die having a silicon based substrate and a second die coupled to the first die. In one example, the second die is formed with compound semiconductor materials. The microelectronic device includes a substrate that is coupled to the first die with a plurality of electrical connections. The substrate including an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher.

公开(公告)号：US10418329B2

公开(公告)日：2019-09-17

申请号：US15774937

申请日：2015-12-11

Applicant: Intel Corporation

Inventor： Eric J. Li ,  Timothy A. Gosselin ,  Yoshihiro Tomita ,  Shawna M. Liff ,  Amram Eitan ,  Mark Saltas

IPC: H01L23/538 ,  H01L23/48 ,  H01L23/13 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L23/31

Abstract: A microelectronic structure includes a microelectronic substrate having a first surface and a cavity extending into the substrate from the microelectronic substrate first surface, a first microelectronic device and a second microelectronic device attached to the microelectronic substrate first surface, and a microelectronic bridge disposed within the microelectronic substrate cavity and attached to the first microelectronic device and to the second microelectronic device. In one embodiment, the microelectronic structure may include a reconstituted wafer formed from the first microelectronic device and the second microelectronic device. In another embodiment, a flux material may extend between the first microelectronic device and the microelectronic bridge and between the second microelectronic device and the microelectronic bridge.