公开(公告)号：US20190157310A1

公开(公告)日：2019-05-23

申请号：US16306295

申请日：2016-07-01

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY ,  KARTHIK JAMBUNATHAN ,  CHANDRA S. MOHAPATRA ,  MAURO J. KOBRINSKY ,  PATRICK MORROW

IPC: H01L27/12 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/088 ,  H01L21/8238 ,  H01L29/775

Abstract: Techniques are disclosed for backside contact resistance reduction for semiconductor devices with metallization on both sides (MOBS). In some embodiments, the techniques described herein provide methods to recover low contact resistance that would otherwise be present with making backside contacts, thereby reducing or eliminating parasitic external resistance that degrades transistor performance. In some embodiments, the techniques include adding an epitaxial deposition of very highly doped crystalline semiconductor material in backside contact trenches to provide enhanced ohmic contact properties. In some cases, a backside source/drain (S/D) etch-stop layer may be formed below the replacement S/D regions of the one or more transistors formed on the transfer wafer (during frontside processing), such that when backside contact trenches are being formed, the backside S/D etch-stop layer may help stop the backside contact etch process before consuming a portion or all of the S/D material. Other embodiments may be described and/or disclosed.

公开(公告)号：US20190043993A1

公开(公告)日：2019-02-07

申请号：US16076550

申请日：2016-03-11

Applicant: INTEL CORPORATION

Inventor： CHANDRA S. MOHAPATRA ,  GLENN A. GLASS ,  ANAND S. MURTHY ,  KARTHIK JAMBUNATHAN ,  WILLY RACHMADY ,  GILBERT DEWEY ,  TAHIR GHANI ,  JACK T. KAVALIEROS

IPC: H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762 ,  H01L21/8252

Abstract: Techniques are disclosed for forming transistors including one or more group III-V semiconductor material nanowires using sacrificial group IV semiconductor material layers. In some cases, the transistors may include a gate-all-around (GAA) configuration. In some cases, the techniques may include forming a replacement fin stack that includes group III-V material layer (such as indium gallium arsenide, indium arsenide, or indium antimonide) formed on a group IV material buffer layer (such as silicon, germanium, or silicon germanium), such that the group IV buffer layer can be later removed using a selective etch process to leave the group III-V material for use as a nanowire in a transistor channel. In some such cases, the group III-V material layer may be grown pseudomorphically to the underlying group IV material, so as to not form misfit dislocations. The techniques may be used to form transistors including any number of nanowires.

公开(公告)号：US20180151733A1

公开(公告)日：2018-05-31

申请号：US15575011

申请日：2015-06-19

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  PATRICK H. KEYS ,  HAROLD W. KENNEL ,  RISHABH MEHANDRU ,  ANAND S. MURTHY ,  KARTHIK JAMBUNATHAN

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/167 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/7848 ,  H01L27/0886 ,  H01L29/0603 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/167 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: Techniques are disclosed for forming p-MOS transistors having one or more carbon-based interface layers between epitaxially grown S/D regions and the channel region. In some cases, the carbon-based interface layer(s) may comprise a single layer having a carbon content of greater than 20% carbon and a thickness of 0.5-8 nm. In some cases, the carbon-based interface layer(s) may comprise a single layer having a carbon content of less than 5% and a thickness of 2-10 nm. In some such cases, the single layer may also comprise boron-doped silicon (Si:B) or boron-doped silicon germanium (SiGe:B). In some cases, one or more additional interface layers may be deposited on the carbon-based interface layer(s), where the additional interface layer(s) comprises Si:B and/or SiGe:B. The techniques can be used to improve short channel effects and improve the effective gate length of a resulting transistor.

公开(公告)号：US20180151732A1

公开(公告)日：2018-05-31

申请号：US15575008

申请日：2015-06-19

Applicant: INTEL CORPORATION

Inventor： RISHABH MEHANDRU ,  ANAND S. MURTHY ,  TAHIR GHANI ,  GLENN A. GLASS ,  KARTHIK JAMBUNATHAN ,  SEAN T. MA ,  CORY E. WEBER

IPC: H01L29/78 ,  H01L29/167 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66 ,  H01L21/306 ,  H01L21/02 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696

Abstract: Techniques are disclosed for resistance reduction in p-MOS transistors having epitaxially grown boron-doped silicon germanium (SiGe:B) S/D regions. The techniques can include growing one or more interface layers between a silicon (Si) channel region of the transistor and the SiGe:B replacement S/D regions. The one or more interface layers may include: a single layer of boron-doped Si (Si:B); a single layer of SiGe:B, where the Ge content in the interface layer is less than that in the resulting SiGe:B S/D regions; a graded layer of SiGe:B, where the Ge content in the alloy starts at a low percentage (or 0%) and is increased to a higher percentage; or multiple stepped layers of SiGe:B, where the Ge content in the alloy starts at a low percentage (or 0%) and is increased to a higher percentage at each step. Inclusion of the interface layer(s) reduces resistance for on-state current flow.

公开(公告)号：US20210083116A1

公开(公告)日：2021-03-18

申请号：US16611920

申请日：2017-06-30

Applicant: INTEL CORPORATION

Inventor： KARTHIK JAMBUNATHAN ,  CORY C. BOMBERGER ,  GLENN A. GLASS ,  ANAND S. MURTHY ,  JU H. NAM ,  TAHIR GHANI

IPC: H01L29/78 ,  H01L27/092

Abstract: Techniques are disclosed for performing silicon (Si) substrate modification to enable formation of a thin, relaxed germanium (Ge)-based layer on the modified Si substrate. The thin, relaxed, Ge-based layer (e.g., having a thickness of at most 500 nm) can then serve as a template for the growth of compressively strained PMOS channel material and tensile strained NMOS channel material to achieve gains in hole and electron mobility, respectively, in the channel regions of the devices. Such a relatively thin Ge-based layer can be formed with suitable surface quality/relaxation levels due to the modification of the Si substrate, where such modification may include depositing a modification layer or performing ion implantation in/on the Si substrate. The modification layer can be characterized by the nucleation of defects which predominantly terminate within the Si substrate or the Ge-based layer, rather than running through to the top of the Ge-based layer.

公开(公告)号：US20200273952A1

公开(公告)日：2020-08-27

申请号：US15930627

申请日：2020-05-13

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY ,  KARTHIK JAMBUNATHAN ,  BENJAMIN CHU-KUNG ,  SEUNG HOON SUNG ,  JACK T. KAVALIEROS ,  TAHIR GHANI ,  HAROLD W. KENNEL

IPC: H01L29/10 ,  H01L21/02 ,  H01L21/22 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: Techniques are disclosed for forming germanium (Ge)-rich channel transistors including one or more dopant diffusion barrier elements. The introduction of one or more dopant diffusion elements into at least a portion of a given source/drain (S/D) region helps inhibit the undesired diffusion of dopant (e.g., B, P, or As) into the adjacent Ge-rich channel region. In some embodiments, the elements that may be included in a given S/D region to help prevent the undesired dopant diffusion include at least one of tin and relatively high silicon. Further, in some such embodiments, carbon may also be included to help prevent the undesired dopant diffusion. In some embodiments, the one or more dopant diffusion barrier elements may be included in an interfacial layer between a given S/D region and the Ge-rich channel region and/or throughout at least a majority of a given S/D region. Numerous embodiments, configurations, and variations will be apparent.

公开(公告)号：US20190214479A1

公开(公告)日：2019-07-11

申请号：US16326844

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： KARTHIK JAMBUNATHAN ,  GLENN A. GLASS ,  ANAND S. MURTHY ,  JACK T. KAVALIEROS ,  SEUNG HOON SUNG ,  BENJAMIN CHU-KUNG ,  TAHIR GHANI

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/417 ,  H01L29/785

Abstract: Integrated circuit transistor structures are disclosed that include a single crystal buffer structure that is lattice matched to the underlying single crystal silicon substrate. The buffer structure may be used to reduce sub-fin leakage in non-planar transistors, but can also be used in planar configurations. In some embodiments, the buffer structure is a single continuous layer of high bandgap dielectric material that is lattice matched to silicon. The techniques below can be utilized on NMOS and PMOS transistors, including any number of group IV and III-V semiconductor channel materials.

公开(公告)号：US20180374951A1

公开(公告)日：2018-12-27

申请号：US15777707

申请日：2015-12-24

Applicant: INTEL CORPORATION

Inventor： KARTHIK JAMBUNATHAN ,  GLENN A. GLASS ,  ANAND S. MURTHY ,  JACOB M. JENSEN ,  DANIEL B. AUBERTINE ,  CHANDRA S. MOHAPATRA

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: Tensile strain is applied to a channel region of a transistor by depositing an amorphous SixGe1-x-yCy alloy in at least one of a source and a drain (S/D) region of the transistors. The amorphous SixGe1-x-yCy alloy is crystallized, thus reducing the unit volume of the alloy. This volume reduction in at least one of the source and the drain region applies strain to a connected channel region. This strain improves electron mobility in the channel. Dopant activation in the source and drain locations is recovered during conversion from amorphous to crystalline structure. Presence of high carbon concentrations reduces dopant diffusion from the source and drain locations into the channel region. The techniques may be employed with respect to both planar and non-planar (e.g., FinFET and nanowire) transistors.

公开(公告)号：US20180331184A1

公开(公告)日：2018-11-15

申请号：US15777553

申请日：2015-12-24

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  KARTHIK JAMBUNATHAN ,  ANAND S. MURTHY ,  CHANDRA S. MOHAPATRA ,  SEIYON KIM ,  JUN SUNG KANG

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/161 ,  H01L29/78 ,  H01L21/764 ,  H01L29/66

CPC classification number: H01L29/1083 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

Abstract: Techniques are disclosed for fabricating semiconductor transistor devices configured with a sub-fin insulation layer that reduces parasitic leakage (i.e., current leakage through a portion of an underlying substrate between a source region and a drain region associated with a transistor). The parasitic leakage is reduced by fabricating transistors with a sacrificial layer in a sub-fin region of the substrate below at least a channel region of the fin. During processing, the sacrificial layer in the sub-fin region is removed and replaced, either in whole or in part, with a dielectric material. The dielectric material increases the electrical resistivity of the substrate between corresponding source and drain portions of the fin, thus reducing parasitic leakage.

公开(公告)号：US20170162447A1

公开(公告)日：2017-06-08

申请号：US15125437

申请日：2014-06-24

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY ,  KARTHIK JAMBUNATHAN

IPC: H01L21/8238 ,  H01L29/10 ,  H01L29/165 ,  H01L29/205 ,  H01L21/84 ,  H01L29/423 ,  H01L29/786 ,  H01L27/12 ,  H01L21/02 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L21/823807 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02603 ,  H01L21/823821 ,  H01L21/8258 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696

Abstract: Techniques are disclosed for forming Ge/SiGe-channel and III-V-channel transistors on the same die. The techniques include depositing a pseudo-substrate of Ge/SiGe or III-V material on a Si or insulator substrate. The pseudo-substrate can then be patterned into fins and a subset of the fins can be replaced by the other of Ge/SiGe or III-V material. The Ge/SiGe fins can be used for p-MOS transistors and the III-V material fins can be used for n-MOS transistors, and both sets of fins can be used for CMOS devices, for example. In some instances, only the channel region of the subset of fins are replaced during, for example, a replacement gate process. In some instances, some or all of the fins may be formed into or replaced by one or more nanowires or nanoribbons.