公开(公告)号：US20180033116A1

公开(公告)日：2018-02-01

申请号：US15550181

申请日：2015-03-18

Applicant: INTEL CORPORATION

Inventor： Kun TIAN ,  David J. COWPERTHWAITE

IPC: G06T1/20

CPC classification number: G06T1/20 ,  G06F8/36 ,  G06F8/41 ,  G06F9/455 ,  G06F9/45558 ,  G06F9/505 ,  G06F17/50 ,  G06T2200/04 ,  G06T2200/08 ,  G06T2200/28

Abstract: An apparatus and method are described for a software agnostic multi-GPU implementation. For example, one embodiment of an apparatus comprises: a plurality of physical graphics processor units (pGPUs) to execute graphics commands; a graphics driver to receive graphics commands generated from applications via a graphics application programming interface (API); a mediator to receive commands directed to pGPU resources from the graphics driver, the mediator to map the plurality of pGPUs into a virtual graphics processor unit (vGPU) visible to the graphics driver, the mediator further including a load balancer to distribute commands received by the vGPU to each of the plurality of pGPUs in accordance with a load balancing policy.

公开(公告)号：US20170123849A1

公开(公告)日：2017-05-04

申请号：US14779234

申请日：2014-06-26

Applicant: INTEL CORPORATION

Inventor： Kun TIAN ,  Zhiyuan LV ,  Yao Zu DONG

IPC: G06F9/48 ,  G06F9/50 ,  G06T1/20 ,  G06F9/455

CPC classification number: G06F9/4881 ,  G06F9/455 ,  G06F9/45558 ,  G06F9/505 ,  G06F9/52 ,  G06F2009/4557 ,  G06F2009/45579 ,  G06T1/20

Abstract: Technologies for scheduling workload submissions for a graphics processing unit (GPU) in a virtualization environment include a GPU scheduler embodied in a computing device. The virtualization environment includes a number of different virtual machines that are configured with a native graphics driver. The GPU scheduler receives GPU commands from the different virtual machines, dynamically selects a scheduling policy, and schedules the GPU commands for processing by the GPU.

公开(公告)号：US20230251912A1

公开(公告)日：2023-08-10

申请号：US18301733

申请日：2023-04-17

Applicant: Intel Corporation

Inventor： Utkarsh Y. KAKAIYA ,  Rajesh SANKARAN ,  Sanjay KUMAR ,  Kun TIAN ,  Philip LANTZ

IPC: G06F9/50 ,  G06F15/76 ,  H04L51/226

CPC classification number: G06F9/5077 ,  G06F9/5038 ,  G06F15/76 ,  H04L51/226 ,  H04T2001/2093 ,  G06F15/17

Abstract: Techniques for scalable virtualization of an Input/Output (I/O) device are described. An electronic device composes a virtual device comprising one or more assignable interface (AI) instances of a plurality of AI instances of a hosting function exposed by the I/O device. The electronic device emulates device resources of the I/O device via the virtual device. The electronic device intercepts a request from the guest pertaining to the virtual device, and determines whether the request from the guest is a fast-path operation to be passed directly to one of the one or more AI instances of the I/O device or a slow-path operation that is to be at least partially serviced via software executed by the electronic device. For a slow-path operation, the electronic device services the request at least partially via the software executed by the electronic device.

公开(公告)号：US20220350499A1

公开(公告)日：2022-11-03

申请号：US17745453

申请日：2022-05-16

Applicant: Intel Corporation

Inventor： Shaopeng HE ,  Yadong LI ,  Anjali Singhai JAIN ,  Kenneth G. KEELS ,  Andrzej SAWULA ,  Kun TIAN ,  Ashok RAJ ,  Rupin H. VAKHARWALA ,  Rajesh M. SANKARAN ,  Saurabh GAYEN ,  Baolu LU ,  Yan ZHAO

IPC: G06F3/06 ,  G06F9/455

Abstract: As described herein, for a selected process identifier and virtual address, a page fault arising from multiple sources can be solved by a one-time operation. The selected process identifier can include a virtual function (VF) identifier or process address space identifier (PASID). In some examples, solving a page fault arising from multiple sources by a one-time operation comprises invoking a page fault handler to determine an address translation.

公开(公告)号：US20220276959A1

公开(公告)日：2022-09-01

申请号：US17695788

申请日：2022-03-15

Applicant: Intel Corporation

Inventor： Yao Zu DONG ,  Kun TIAN ,  Fengguang WU ,  Jingqi LIU

IPC: G06F12/0802 ,  G06F3/06

Abstract: Various embodiments are generally directed to virtualized systems. A first guest memory page may be identified based at least in part on a number of accesses to a page table entry for the first guest memory page in a page table by an application executing in a virtual machine (VM) on the processor, the first guest memory page corresponding to a first byte-addressable memory. The execution of the VM and the application on the processor may be paused. The first guest memory page may be migrated to a target memory page in a second byte-addressable memory, the target memory page comprising one of a target host memory page and a target guest memory page, the second byte-addressable memory having an access speed faster than an access speed of the first byte-addressable memory.

公开(公告)号：US20210373934A1

公开(公告)日：2021-12-02

申请号：US17404897

申请日：2021-08-17

Applicant: Intel Corporation

Inventor： Sanjay KUMAR ,  Rajesh M. SANKARAN ,  Gilbert NEIGER ,  Philip R. LANTZ ,  Jason W. BRANDT ,  Vedvyas SHANBHOGUE ,  Utkarsh Y. KAKAIYA ,  Kun TIAN

IPC: G06F9/455 ,  G06F9/30 ,  G06F12/1045 ,  G06F12/109

Abstract: Implementations of the disclosure provide a processing device comprising an address translation circuit to intercept a work request from an I/O device. The work request comprises a first ASID to map to a work queue. A second ASID of a host is allocated for the first ASID based on the work queue. The second ASID is allocated to at least one of: an ASID register for a dedicated work queue (DWQ) or an ASID translation table for a shared work queue (SWQ). Responsive to receiving a work submission from the SVM client to the I/O device, the first ASID of the application container is translated to the second ASID of the host machine for submission to the I/O device using at least one of: the ASID register for the DWQ or the ASID translation table for the SWQ based on the work queue associated with the I/O device.

公开(公告)号：US20190295210A1

公开(公告)日：2019-09-26

申请号：US16305865

申请日：2016-07-02

Applicant: INTEL CORPORATION

Inventor： Dinyu PEI ,  Kun TIAN

IPC: G06T1/20 ,  G09G5/00 ,  G09G5/14 ,  G09G5/36

Abstract: A display engine comprises a surface splitter to generate frame buffer coordinates to split frame buffer data into a plurality of regions, each corresponding to a frame buffer coordinate, a pipeline, including a plurality of pipes, to receive the frame buffer coordinates, wherein two or more of the plurality of pipes operate in parallel to process frame buffer data corresponding to a region of the frame buffer identified by the frame buffer coordinates, a first of a plurality of transcoders to merge the frame buffer data from each of the two or more pipes into an output signal whenever the display engine is operating in a multi-pipe collaboration mode and a multiplexer (Mux) and multi-stream arbiter to control an order of transmission of the frame buffer data from each of the two or more pipes to the first transcoder based on a fetch order received from the surface splitter.

公开(公告)号：US20240126695A1

公开(公告)日：2024-04-18

申请号：US18392310

申请日：2023-12-21

Applicant: Intel Corporation

Inventor： Yao Zu DONG ,  Kun TIAN ,  Fengguang WU ,  Jingqi LIU

IPC: G06F12/0802 ,  G06F3/06

CPC classification number: G06F12/0802 ,  G06F3/0604 ,  G06F3/0647 ,  G06F3/0667 ,  G06F3/0673 ,  G06F2212/651

Abstract: Various embodiments are generally directed to virtualized systems. A first guest memory page may be identified based at least in part on a number of accesses to a page table entry for the first guest memory page in a page table by an application executing in a virtual machine (VM) on the processor, the first guest memory page corresponding to a first byte-addressable memory. The execution of the VM and the application on the processor may be paused. The first guest memory page may be migrated to a target memory page in a second byte-addressable memory, the target memory page comprising one of a target host memory page and a target guest memory page, the second byte-addressable memory having an access speed faster than an access speed of the first byte-addressable memory.

公开(公告)号：US20220350714A1

公开(公告)日：2022-11-03

申请号：US17868596

申请日：2022-07-19

Applicant: Intel Corporation

Inventor： Nrupal JANI ,  Manasi DEVAL ,  Anjali Singhai JAIN ,  Parthasarathy SARANGAM ,  Mitu AGGARWAL ,  Neerav PARIKH ,  Alexander H. DUYCK ,  Kiran PATIL ,  Rajesh M. SANKARAN ,  Sanjay K. KUMAR ,  Utkarsh Y. KAKAIYA ,  Philip LANTZ ,  Kun TIAN

IPC: G06F11/20 ,  G06F3/06 ,  G06F13/16 ,  G06F13/42 ,  G06F13/40 ,  G06F15/173 ,  G06F9/455 ,  G06F9/48

Abstract: Examples may include a method of instantiating a virtual machine, instantiating a virtual device to transmit data to and receive data from assigned resources of a shared physical device; and assigning the virtual device to the virtual machine, the virtual machine to transmit data to and receive data from the physical device via the virtual device.

公开(公告)号：US20210263755A1

公开(公告)日：2021-08-26

申请号：US17256204

申请日：2018-11-30

Applicant: INTEL CORPORATION

Inventor： Kun TIAN ,  Ankur SHAH ,  David COWPERTHWAITE ,  Zhi WANG ,  Zhenyu WANG ,  Kalyan KONDAPALLY ,  Jonathan BLOOMFIELD ,  Wei ZHANG

IPC: G06F9/451 ,  G06F9/455 ,  G06F9/4401 ,  G06F3/14 ,  G09G5/00

Abstract: Apparatus and method for implementing a virtual display. For example, one embodiment of a graphics processing apparatus comprises at least one configuration register to store framebuffer descriptor information for a first guest running on a first virtual machine (VM) in a virtualized execution environment of a host processor, the framebuffer descriptor information to indicate one or more display pipes assigned to the first guest; and execution circuitry to execute a first driver assigned to the first guest, the first guest to use the first driver to display a framebuffer in a plane associated with one of the display pipes in accordance with the framebuffer descriptor information.