公开(公告)号：US20230317681A1

公开(公告)日：2023-10-05

申请号：US17709481

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Sonja Koller ,  Vishnu Prasad ,  Bernd Waidhas ,  Eduardo De Mesa ,  Lizabeth Keser ,  Thomas Wagner ,  Mohan Prashanth Javare Gowda ,  Abdallah Bacha ,  Jan Proschwitz

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/427 ,  H01L23/367 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/3736 ,  H01L23/427 ,  H01L24/16 ,  H01L24/32 ,  H01L23/367 ,  H01L25/50 ,  H01L2225/06589 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2224/73203 ,  H01L2224/32245 ,  H01L2224/16146 ,  H01L2224/14152 ,  H01L2224/1416 ,  H01L24/14 ,  H01L24/73

Abstract: Disclosed herein are microelectronic packages having thermally conductive layers and methods for manufacturing the same. The microelectronics packages may include a substrate and a plurality of dies connected to the substrate and/or each other to form a die stack. The dies may have a perimeter. A thermally conductive layer may be located in between the respective dies. The thermally conductive layers may extend past at least a portion of the perimeters, thereby providing enhanced cooling of the die stack.

公开(公告)号：US20230317618A1

公开(公告)日：2023-10-05

申请号：US17707157

申请日：2022-03-29

Applicant: Intel Corporation

Inventor： Carlton Hanna ,  Georg Seidemann ,  Eduardo De Mesa ,  Abdallah Bacha ,  Lizabeth Keser

IPC: H01L23/538 ,  H01L23/14 ,  H01L21/48 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/145 ,  H01L21/4857 ,  H01L21/486 ,  H01L25/0655 ,  H01L23/49816

Abstract: An electronic device comprises a substrate including an organic material; a glass bridge die included in the substrate, the glass bridge die including electrically conductive interconnect; and a first integrated circuit (IC) die and at least a second IC die arranged on a surface of the substrate and including bonding pads connected to the interconnect of the glass bridge die.

公开(公告)号：US20230317551A1

公开(公告)日：2023-10-05

申请号：US17708890

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Vishnu Prasad ,  Abdallah Bacha ,  Mohan Prashanth Javare Gowda ,  Lizabeth Keser ,  Thomas Wagner ,  Bernd Waidhas ,  Sonja Koller ,  Eduardo De Mesa ,  Jan Proschwitz

IPC: H01L23/373 ,  H01L25/18 ,  H01L21/48

CPC classification number: H01L23/3736 ,  H01L25/18 ,  H01L21/4896

Abstract: Disclosed herein are microelectronics packages that include thermal pillars for at least localized extraction of generated heat and methods for manufacturing the same. The microelectronics packages may include a substrate and a plurality of dies stacked on the substrate with at least one of the plurality of dies connected to the substrate. A heat spreader may be located proximate at least a portion of the plurality of dies. Respective thermal pillars from a plurality of thermal pillars may extend from at least one of the plurality dies to the heat spreader. Each of the plurality of thermal pillars may define a respective pathway from at least one of the plurality of dies to the heat spreader.

公开(公告)号：US20250132259A1

公开(公告)日：2025-04-24

申请号：US18989232

申请日：2024-12-20

Applicant: Intel Corporation

Inventor： Bernd Waidhas ,  Carlton Hanna ,  Stephen Morein ,  Lizabeth Keser ,  Georg Seidemann

IPC: H01L23/538 ,  H01L23/50 ,  H01L23/522

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate, having a surface, including a first conductive pathway electrically coupled to a power source; a first microelectronic component, having an active side electrically coupled to the surface of the package substrate and an opposing back side, surrounded by an insulating material; a second microelectronic component, having an active side electrically coupled to the surface of the package substrate and an opposing back side, surrounded by the insulating material and including a through-substrate via (TSV) electrically coupled to the first conductive pathway; and a redistribution layer (RDL), on the insulating material, including a second conductive pathway electrically coupling the TSV, the second surface of the second microelectronic component, and the second surface of the first microelectronic component.

公开(公告)号：US12211796B2

公开(公告)日：2025-01-28

申请号：US17355747

申请日：2021-06-23

Applicant: Intel Corporation

Inventor： Bernd Waidhas ,  Carlton Hanna ,  Stephen Morein ,  Lizabeth Keser ,  Georg Seidemann

IPC: H01L23/538 ,  H01L23/50 ,  H01L23/522

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate including a first conductive pathway electrically coupled to a power source; a first microelectronic component, embedded in an insulating material on the surface of the package substrate, including a through-substrate via (TSV) electrically coupled to the first conductive pathway; a second microelectronic component embedded in the insulating material; and a redistribution layer on the insulating material including a second conductive pathway electrically coupling the TSV, the second microelectronic component, and the first microelectronic component.

公开(公告)号：US11955395B2

公开(公告)日：2024-04-09

申请号：US17855674

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Lizabeth Keser ,  Bernd Waidhas ,  Thomas Ort ,  Thomas Wagner

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/522 ,  H01L49/02

CPC classification number: H01L23/3114 ,  H01L21/568 ,  H01L23/5226 ,  H01L24/11 ,  H01L24/14 ,  H01L24/96 ,  H01L28/10 ,  H01L28/40 ,  H01L2224/02379 ,  H01L2924/19011

Abstract: A semiconductor device and method of including peripheral devices into a package is disclosed. In one example, a peripheral device includes a passive device such as a capacitor or an inductor. Examples are shown that include a peripheral device that is substantially the same thickness as a die or a die assembly. Examples are further shown that use this configuration in a fan out process to form semiconductor devices.

公开(公告)号：US20230282615A1

公开(公告)日：2023-09-07

申请号：US17685871

申请日：2022-03-03

Applicant: Intel Corporation

Inventor： Thomas Wagner ,  Abdallah Bacha ,  Vishnu Prasad ,  Mohan Prashanth Javare Gowda ,  Bernd Waidhas ,  Sonja Koller ,  Eduardo De Mesa ,  Jan Proschwitz ,  Lizabeth Keser

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L25/0657 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/15311

Abstract: A microelectronic assembly is provided, comprising: an interposer having a first side and a second side opposite to the first side; a plurality of integrated circuit (IC) dies in a plurality of layers on the first side of the interposer, the plurality of IC dies being encased by a dielectric material; a package substrate on the second side of the interposer; a plurality of conductive vias through the plurality of layers; and redistribution layers adjacent to the layers in the plurality of layers, at least some of the redistribution layers comprising conductive traces coupling the conductive vias to the IC dies.

公开(公告)号：US20220415806A1

公开(公告)日：2022-12-29

申请号：US17355747

申请日：2021-06-23

Applicant: Intel Corporation

Inventor： Bernd Waidhas ,  Carlton Hanna ,  Stephen Morein ,  Lizabeth Keser ,  Georg Seidemann

IPC: H01L23/538 ,  H01L23/522 ,  H01L23/50

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate including a first conductive pathway electrically coupled to a power source; a first microelectronic component, embedded in an insulating material on the surface of the package substrate, including a through-substrate via (TSV) electrically coupled to the first conductive pathway; a second microelectronic component embedded in the insulating material; and a redistribution layer on the insulating material including a second conductive pathway electrically coupling the TSV, the second microelectronic component, and the first microelectronic component.

公开(公告)号：US20220415805A1

公开(公告)日：2022-12-29

申请号：US17355726

申请日：2021-06-23

Applicant: Intel Corporation

Inventor： Bernd Waidhas ,  Carlton Hanna ,  Stephen Morein ,  Lizabeth Keser ,  Georg Seidemann

IPC: H01L23/538 ,  H01L23/50 ,  H01L23/522 ,  H01L23/36

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate, having a surface, including a first conductive pathway electrically coupled to a power source; an insulating material on the surface of the package substrate; a first microelectronic component, having a first surface facing the package substrate and an opposing second surface, embedded in the insulating material; a second microelectronic component, having a first surface facing the package substrate and an opposing second surface, embedded in the insulating material; a redistribution layer on the insulating material including a second conductive pathway electrically coupled to the second surface of the second microelectronic component and the second surface of the first microelectronic component; and a wire bond electrically coupling the first and the second conductive pathways.

公开(公告)号：US12057364B2

公开(公告)日：2024-08-06

申请号：US17991503

申请日：2022-11-21

Applicant: Intel Corporation

Inventor： Lizabeth Keser ,  Thomas Ort ,  Thomas Wagner ,  Bernd Waidhas

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66 ,  H01L21/78 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L23/3192 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L22/14 ,  H01L23/3114 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L23/3128 ,  H01L2224/18 ,  H01L2224/214 ,  H01L2224/95001

Abstract: A semiconductor device and method is disclosed. Devices shown include a die coupled to an integrated routing layer, wherein the integrated routing layer includes a first width that is wider than the die. Devices shown further included a molded routing layer coupled to the integrated routing layer.