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    Systems And Methods For Correcting Errors in Code For Circuit Designs
    11.
    发明公开
    Systems And Methods For Correcting Errors in Code For Circuit Designs 审中-公开

    公开(公告)号：US20230222275A1

    公开(公告)日：2023-07-13

    申请号：US18122612

    申请日：2023-03-16

    Applicant: Intel Corporation

    Inventor： Gregg Baeckler ,  Mahesh A. Iyer ,  Martin Langhammer

    IPC: G06F30/327

    CPC classification number: G06F30/327 ,  G06F2111/04

    Abstract: A method is provided for processing code for a circuit design for an integrated circuit using a computer system. The method includes receiving at least a portion of the code for the circuit design for the integrated circuit, wherein the portion of the code comprises an error or has incomplete constraints, making an assumption about the error and the missing constraints using a computer aid design tool, and generating a revised circuit design for the integrated circuit with the error corrected and any missing constraints added based on the assumption and based on the code using the computer aided design tool and a library of components for circuit designs.

    On-Die Aging Measurements for Dynamic Timing Modeling
    12.
    发明申请
    On-Die Aging Measurements for Dynamic Timing Modeling 有权

    公开(公告)号：US20230129176A1

    公开(公告)日：2023-04-27

    申请号：US18086616

    申请日：2022-12-21

    Applicant: Intel Corporation

    Inventor： Dheeraj Subbareddy ,  Ankireddy Nalamalpu ,  Mahesh A. Iyer ,  Dhananjay Raghavan

    IPC: G01R31/26 ,  G01R31/317 ,  G01R31/3193 ,  G01R31/28 ,  G01R31/30 ,  G01R31/3185

    Abstract: A method includes mapping an aging measurement circuit (AMC) into the core fabric of an FPGA and operating the AMC for a select time period. During the select period of time, the AMC counts transition of a signal propagating through the AMC. Timing information based on the counted transitions is stored in a timing model in a memory. The timing information represents an aging characteristic of the core fabric at a time that the AMC is operated. An EDA toolchain uses the timing information in the timing model to generate a timing guard-band for the configurable IC die. The AMC is removed from the core fabric and another circuit device is mapped and fitted into the core fabric using the generated timing guard-band models. The circuit device is operated in the configurable IC die based on the timing guard-band models.

    DYNAMIC LOADLINES FOR PROGRAMMABLE FABRIC DEVICES
    14.
    发明申请
    DYNAMIC LOADLINES FOR PROGRAMMABLE FABRIC DEVICES 有权

    公开(公告)号：US20220114316A1

    公开(公告)日：2022-04-14

    申请号：US17559607

    申请日：2021-12-22

    Applicant: Intel Corporation

    Inventor： Yuet Li ,  Ankireddy Nalamalpu ,  Atul Maheshwari ,  MD Altaf Hossain ,  Mahesh K. Kumashikar ,  Mahesh A. Iyer

    IPC: G06F30/343 ,  G06F1/26

    Abstract: Systems or methods of the present disclosure may provide for determining a loadline for operation of a programmable logic fabric where the loadline is based at least in part on design configuration details for a design or a configuration rather for generic deployment of the programmable logic device. The loadline may be determined using software modeling for the design or configuration. Additionally or alternatively, the loadline may be determined using runtime testing and sensing of real-world parameters. This determination based on real-world parameters of a deployment of the configuration or design is based on a determination of a step load for the design or configuration.

    METHODS AND APPARATUS TO INSERT BUFFERS IN A DATAFLOW GRAPH
    17.
    发明申请
    METHODS AND APPARATUS TO INSERT BUFFERS IN A DATAFLOW GRAPH 审中-公开

    公开(公告)号：US20190229996A1

    公开(公告)日：2019-07-25

    申请号：US16370934

    申请日：2019-03-30

    Applicant: Intel Corporation

    Inventor： Kermin E. ChoFleming, JR. ,  Jesmin Jahan Tithi ,  Suresh Srinivasan ,  Mahesh A. Iyer

    IPC: H04L12/24 ,  H04L12/26 ,  H04L12/861

    Abstract: Disclosed examples to insert buffers in dataflow graphs include: a backedge filter to remove a backedge between a first node and a second node of a dataflow graph, the first node representing a first operation of the dataflow graph, the second node representing a second operation of the dataflow graph; a latency calculator to determine a critical path latency of a critical path of the dataflow graph that includes the first node and the second node, the critical path having a longer latency to completion relative to a second path that terminates at the second node; a latency comparator to compare the critical path latency to a latency sum of a buffer latency and a second path latency, the second path latency corresponding to the second path; and a buffer allocator to insert one or more buffers in the second path based on the comparison performed by the latency comparator.

    METHODS FOR VERIFYING RETIMED CIRCUITS WITH DELAYED INITIALIZATION
    18.
    发明申请
    METHODS FOR VERIFYING RETIMED CIRCUITS WITH DELAYED INITIALIZATION 审中-公开

    公开(公告)号：US20180137226A1

    公开(公告)日：2018-05-17

    申请号：US15354809

    申请日：2016-11-17

    Applicant: Intel Corporation

    Inventor： Mahesh A. Iyer

    IPC: G06F17/50

    CPC classification number: G06F17/5031 ,  G06F1/24 ,  G06F17/504 ,  G06F17/505 ,  G06F17/5054 ,  G06F17/5077 ,  G06F17/5081

    Abstract: Circuit design computing equipment may perform register moves within a circuit design. When moving the registers, counter values may be maintained for non-justifiable elements. The counter values may be maintained and updated on a per element, per clock domain basis to account for register moves across the corresponding non-justifiable elements. The maximum counter value for each clock domain may be chosen as an adjustment value that is used to generate a sequence for resetting the modified circuit design after the register moves. The adjustment value may be bound by a user-specified maximum value. This retiming operation may also be verified by performing rewind verification. The rewind verification involves retiming the retimed circuit back to the original circuit, while respecting the counter values. If verification succeeds, the circuit design may be reset using a smaller adjustment value. If verification fails, a correct counter value may be suggested for each clock domain.

    Temperature Control Systems And Methods For Integrated Circuits
    19.
    发明申请
    Temperature Control Systems And Methods For Integrated Circuits 有权

    公开(公告)号：US20220215147A1

    公开(公告)日：2022-07-07

    申请号：US17703181

    申请日：2022-03-24

    Applicant: Intel Corporation

    Inventor： Teik Wah Lim ,  Rajiv Mongia ,  Archanna Srinivasan ,  Mahesh A. Iyer

    IPC: G06F30/32 ,  G06F30/343

    Abstract: An integrated circuit system includes a temperature sensor circuit that generates an output indicative of a temperature in an integrated circuit. The integrated circuit system also includes a temperature management controller circuit that compares the temperature indicated by the output of the temperature sensor circuit to a temperature threshold. The integrated circuit system further includes temperature reduction circuitry and/or design compilation techniques and partial or full reconfiguration that controls the temperature in the integrated circuit system. The temperature management controller circuit causes the temperature reduction circuitry to reduce the temperature in response to the temperature indicated by the output of the temperature sensor circuit exceeding the temperature threshold. The temperature sensor circuit, the temperature management controller circuit, and the temperature reduction circuitry may be implemented by soft logic circuits, hard logic circuits, or any combination thereof.

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