公开(公告)号：US20220068861A1

公开(公告)日：2022-03-03

申请号：US17523787

申请日：2021-11-10

Applicant: Intel Corporation

Inventor： Pramod MALATKAR ,  Weng Hong TEH ,  John S. GUZEK ,  Robert L. SANKMAN

IPC: H01L23/00 ,  H01L27/08 ,  H01L23/48 ,  H01L23/538

Abstract: A packaged semiconductor die with a bumpless die-package interface and methods of fabrication are described. For example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines, one of which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate. In another example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines with a layer of conductive vias disposed thereon. At least one of the conductive lines is coupled directly to a conductive via of the semiconductor die which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate.

公开(公告)号：US20210082798A1

公开(公告)日：2021-03-18

申请号：US16575307

申请日：2019-09-18

Applicant: Intel Corporation

Inventor： Xiao LU ,  Jiongxin LU ,  Christopher COMBS ,  Alexander HUETTIS ,  John HARPER ,  Jieping ZHANG ,  Nachiket R. RARAVIKAR ,  Pramod MALATKAR ,  Steven A. KLEIN ,  Carl DEPPISCH ,  Mohit SOOD

IPC: H01L23/498 ,  B23K3/06 ,  H01L23/538

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first substrate; a second substrate; and an array of interconnects electrically coupling the first substrate to the second substrate. In an embodiment, the array of interconnects comprises first interconnects, wherein the first interconnects have a first volume and a first material composition, and second interconnects, wherein the second interconnects have a second volume and a second material composition, and wherein the first volume is different than the second volume and/or the first material composition is different than the second material composition.

公开(公告)号：US20200066655A1

公开(公告)日：2020-02-27

申请号：US16611830

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Feras EID ,  Venkata Suresh R. GUTHIKONDA ,  Shankar DEVASENATHIPATHY ,  Chandra M. JHA ,  Je-Young CHANG ,  Kyle YAZZIE ,  Prasanna RAGHAVAN ,  Pramod MALATKAR

IPC: H01L23/00 ,  H01L23/544 ,  H05K1/02 ,  H05K1/18 ,  H01L25/065 ,  H01L21/50

Abstract: A foundation layer having a stiffener and methods of forming a stiffener are described. One or more dies are formed over the foundation layer. Each die has a front side surface that is electrically coupled to the foundation layer and a back side surface that is opposite from the front side surface. A stiffening layer (or a stiffener) is formed on the back side surface of at least one of the dies. The stiffening layer may be directly coupled to the back side surface of the one or more dies without an adhesive layer. The stiffening layer may include one or more materials, including at least one of a metal, a metal alloy, and a ceramic. The stiffening layer may be formed to reduce warpage based on the foundation layer and the dies. The one or more materials of the stiffening layer can be formed using a cold spray.

公开(公告)号：US20190051615A1

公开(公告)日：2019-02-14

申请号：US16075513

申请日：2016-04-02

Applicant: Intel Corporation

Inventor： Vijay K. NAIR ,  Pramod MALATKAR

IPC: H01L23/552 ,  H01L21/48 ,  H01L23/367 ,  H01L23/498 ,  H01L23/00

Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing an organic stiffener with an EMI shield for RF integration. For instance, in accordance with one embodiment, there is an apparatus having therein: a substrate layer having electrical traces and a ground plane therein; a functional semiconductor die electrically interfaced to the electrical traces of the substrate layer; a heat pipe thermally interfaced to a top surface of the functional semiconductor die; one or more interposers of an organic dielectric material electrically connected to the ground plane of the substrate layer and electrically connected to the heat pipe; in which the one or more interposers form the electromagnetic shield to electrically shield the functional semiconductor die; and further in which the one or more interposers form the organic stiffener are to mechanically retain the substrate layer in a planer form. Other related embodiments are disclosed.

公开(公告)号：US20190043772A1

公开(公告)日：2019-02-07

申请号：US16075120

申请日：2016-04-02

Applicant: Intel Corporation

Inventor： Purushotham Kaushik MUTHUR SRINATH ,  Pramod MALATKAR ,  Sairam AGRAHARAM ,  Chandra M. JHA ,  Arnab CHOUDHURY ,  Nachiket R. RARAVIKAR

IPC: H01L23/26 ,  H01L23/433

Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing a thermal solution for 3D packaging. For instance, in accordance with one embodiment, there is an apparatus having therein: a substrate layer having electrical traces therein; a first layer functional silicon die electrically interfaced to the electrical traces of the substrate layer, the first layer functional silicon die having a first thermal pad integrated thereupon; a second layer functional silicon die positioned above the first layer functional silicon die, the second layer functional silicon die having a second thermal pad integrated thereupon; and a conductivity layer positioned between the first layer functional silicon die and the second layer functional silicon die, wherein the conductivity layer is to: (i) electrically join the second layer functional silicon die to the first layer functional silicon die and (ii) bond the first thermal pad of the first layer functional silicon die to the second thermal pad of the second layer functional silicon die via solder. Other related embodiments are disclosed.

公开(公告)号：US20180376591A1

公开(公告)日：2018-12-27

申请号：US16118990

申请日：2018-08-31

Applicant: Intel Corporation

Inventor： Yoshihiro TOMITA ,  Joshua D. HEPPNER ,  Shawna M. LIFF ,  Pramod MALATKAR

IPC: H05K1/03 ,  H05K3/00 ,  A41D13/00 ,  A43B1/00 ,  A43B3/00 ,  H05K1/11 ,  H05K1/18 ,  H05K3/32 ,  A41D1/00

Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing a magnetic particle embedded flexible substrate, a printed flexible substrate for a magnetic tray, or an electro-magnetic carrier for magnetized or ferromagnetic flexible substrates. For instance, in accordance with one embodiment, there are means disclosed for fabricating a flexible substrate having one or more electrical interconnects to couple with leads of an electrical device; integrating magnetic particles or ferromagnetic particles into the flexible substrate; supporting the flexible substrate with a carrier plate during one or more manufacturing processes for the flexible substrate, in which the flexible substrate is held flat against the carrier plate by an attractive magnetic force between the magnetic particles or ferromagnetic particles integrated with the flexible substrate and a complementary magnetic attraction of the carrier plate; and removing the flexible substrate from the carrier plate subsequent to completion of the one or more manufacturing processes for the flexible substrate. Other related embodiments are disclosed.

公开(公告)号：US20180322993A1

公开(公告)日：2018-11-08

申请号：US15770747

申请日：2015-12-21

Applicant: Intel Corporation

Inventor： Kyle YAZZIE ,  Pramod MALATKAR

IPC: H01F7/02 ,  B25J15/06 ,  G01R1/067

CPC classification number: H01F7/0257 ,  B25J15/0608 ,  B81C1/00 ,  G01R1/06705

Abstract: A magnetic pick and place probe includes an outer sheath, an inner sheath to vertically slide within the outer sheath, None or more sheath magnets attached to a bottom end of the inner sheath and a tip positioned at a bottom end of the outer sheath to simultaneously pick up an array of magnets for placement on a substrate.

公开(公告)号：US20170269017A1

公开(公告)日：2017-09-21

申请号：US15075083

申请日：2016-03-18

Applicant: Intel Corporation

Inventor： Steven A. KLEIN ,  Rajendra C. DIAS ,  David C. MCCOY ,  Lars D. SKOGLUND ,  Vijay SUBRAMANIAN ,  Aleksander ALEKSOV ,  Pramod MALATKAR ,  Ravindranath V. MAHAJAN ,  Robert L. SANKMAN

IPC: G01N27/20

CPC classification number: G01N27/20 ,  G01L1/04 ,  G01L1/18 ,  G01L1/22 ,  G01N3/08 ,  G01N2033/0078 ,  G01N2033/0095 ,  G01N2203/0042 ,  G01N2203/0044 ,  G01N2203/0062

Abstract: Embodiments are generally directed to air bladder based mechanical testing for stretchable electronics. An embodiment of a system includes an inflatable bladder to apply mechanical force to a stretchable electronics device by the inflation and deflation of the inflatable bladder; a valve unit to control fluid pressure applied to the inflatable bladder; and a control unit to control inflation and deflation of the inflatable bladder.