公开(公告)号：US09820386B2

公开(公告)日：2017-11-14

申请号：US15074064

申请日：2016-03-18

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Rahul Jain ,  Robert Alan May ,  Sheng Li ,  Sri Ranga Sai Boyapati

IPC: H05K3/00 ,  H05K1/09 ,  H05K1/03

CPC classification number: H05K3/0041 ,  H05K1/0313 ,  H05K1/09 ,  H05K3/0055 ,  H05K3/3452 ,  H05K2203/0502 ,  H05K2203/0548 ,  H05K2203/0562 ,  H05K2203/0588 ,  H05K2203/095

Abstract: A method of forming an electronic assembly. The method includes covering a patterned conductive layer that is on a dielectric layer with a solder resist; depositing a metal layer on to the solder resist; depositing a photo resist onto the metal layer; patterning the photo resist; etching the metal layer that is exposed from the photo resist to form a metal mask; removing the photo resist; and plasma etching the solder resist that is exposed from the metal mask. An electronic assembly for securing for an electronic card. The electronic assembly includes a patterned conductive layer that is on a dielectric layer; and a solder resist covering the patterned conductive layer and the dielectric layer, wherein the solder resist includes openings that expose the patterned conductive layer, wherein the openings in the solder resist only have organic material on side walls of the respective openings.

公开(公告)号：US12014989B2

公开(公告)日：2024-06-18

申请号：US18091048

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Robert Alan May ,  Wei-Lun Kane Jen ,  Jonathan L. Rosch ,  Islam A. Salama ,  Kristof Darmawikarta

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/683 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/16227

Abstract: A device and method for providing enhanced bridge structures is disclosed. A set of conducting and insulating layers are deposited and lithographically processed. The conducting layers have uFLS routing. A bridge with uFLS contacts and die disposed on the underlying structure such that the die are connected with the uFLS contacts and uFLS routing. For core-based structures, the layers are formed after the bridge is placed on the underlying structure and the die connected to the bridge through intervening conductive layers. For coreless structures, the layers are formed over the bridge and carrier, which is removed prior to bonding the die to the bridge, and the die bonded directly to the bridge.

公开(公告)号：US11862619B2

公开(公告)日：2024-01-02

申请号：US16649923

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Srinivas Pietambaram ,  Robert Alan May ,  Kristof Darmawikarta ,  Hiroki Tanaka ,  Rahul N. Manepalli ,  Sri Ranga Sai Boyapati

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49866 ,  H01L23/5385 ,  H01L23/5389 ,  H01L25/0652 ,  H01L24/14 ,  H01L2224/1403

Abstract: Techniques for a patch to couple one or more surface dies to an interposer or motherboard are provided. In an example, the patch can include multiple embedded dies. In an example, a microelectronic device can be formed to include a patch on an interposer, where the patch can include multiple embedded dies and each die can have a different thickness.

公开(公告)号：US11817390B2

公开(公告)日：2023-11-14

申请号：US18090795

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  Ram Viswanath ,  Xavier Francois Brun ,  Tarek A. Ibrahim ,  Jason M. Gamba ,  Manish Dubey ,  Robert Alan May

IPC: H01L23/538 ,  H01L23/367 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/5381 ,  H01L23/3185 ,  H01L23/367 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16 ,  H01L2224/16227

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.

公开(公告)号：US11430740B2

公开(公告)日：2022-08-30

申请号：US16474026

申请日：2017-03-29

Applicant: Intel Corporation

Inventor： Robert Alan May ,  Islam A. Salama ,  Sri Ranga Sai Boyapati ,  Sheng Li ,  Kristof Darmawikarta ,  Robert L. Sankman ,  Amruthavalli Pallavi Alur

IPC: H01L23/52 ,  H01L23/31 ,  H01L25/07 ,  H01L25/11 ,  H01L23/538 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L25/065

Abstract: Microelectronic devices with an embedded die substrate on an interposer are described. For example, a microelectronic device includes a substrate housing an embedded die. At least one surface die is retained above a first outermost surface of the substrate. An interposer is retained proximate a second outermost surface of the substrate.

公开(公告)号：US11244912B2

公开(公告)日：2022-02-08

申请号：US16481385

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Sai Vadlamani ,  Aleksandar Aleksov ,  Rahul Jain ,  Kyu Oh Lee ,  Kristof Kuwawi Darmawikarta ,  Robert Alan May ,  Sri Ranga Sai Boyapati ,  Telesphor Kamgaing

IPC: H01L21/48 ,  H01L23/66 ,  H01L23/498 ,  H01L23/00

Abstract: Semiconductor packages having a first layer interconnect portion that includes a coaxial interconnect between a die and a package substrate are described. In an example, the package substrate includes a substrate-side coaxial interconnect electrically connected to a signal line. The die is mounted on the package substrate and includes a die-side coaxial interconnect coupled to the substrate-side coaxial interconnect. The coaxial interconnects can be joined by a solder bond between respective central conductors and shield conductors.

公开(公告)号：US11233009B2

公开(公告)日：2022-01-25

申请号：US16832150

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Praneeth Kumar Akkinepally ,  Frank Truong ,  Jason M. Gamba ,  Robert Alan May

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/31

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a microelectronic component embedded in the package substrate, the microelectronic component including: a substrate having a surface, where the substrate includes a conductive pathway and a mold material region at the surface, where the mold material region includes a through-mold via (TMV) electrically coupled to the conductive pathway, and where the mold material region is at the second surface of the package substrate; and a die conductively coupled, at the second surface of the package substrate, to the package substrate and to the TMV of the microelectronic component.

公开(公告)号：US20210305162A1

公开(公告)日：2021-09-30

申请号：US16829396

申请日：2020-03-25

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  Ram Viswanath ,  Xavier Francois Brun ,  Tarek A. Ibrahim ,  Jason M. Gamba ,  Manish Dubey ,  Robert Alan May

IPC: H01L23/538 ,  H01L23/367 ,  H01L23/31 ,  H01L23/00

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.

公开(公告)号：US20210280517A1

公开(公告)日：2021-09-09

申请号：US16322423

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Robert Alan May ,  Wei-Lun Kane Jen ,  Jonathan L. Rosch ,  Islam A. Salama ,  Kristof Darmawikarta

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48 ,  H01L25/00

Abstract: A device and method for providing enhanced bridge structures is disclosed. A set of conducting and insulating layers are deposited and lithographically processed. The conducting layers have uFLS routing. A bridge with uFLS contacts and die disposed on the underlying structure such that the die are connected with the uFLS contacts and uFLS routing. For core-based structures, the layers are formed after the bridge is placed on the underlying structure and the die connected to the bridge through intervening conductive layers. For coreless structures, the layers are formed over the bridge and carrier, which is removed prior to bonding the die to the bridge, and the die bonded directly to the bridge.

公开(公告)号：US11069620B2

公开(公告)日：2021-07-20

申请号：US16474585

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Robert Alan May ,  Kristof Darmawikarta ,  Sri Ranga Sai Sai Boyapati

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/29 ,  H01L23/538 ,  H01L23/00

Abstract: A die interconnect substrate comprises a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate comprises a multilayer substrate structure comprising a substrate interconnect. The bridge die is embedded in the multilayer substrate structure. The substrate interconnect extends from a level above the bridge die to a level below the bridge die. The multilayer substrate structure further comprises an electrically insulating layer comprising a first electrically insulating material. The multilayer substrate structure further comprises an electrically insulating filler structure located laterally between the bridge die and the electrically insulating layer, wherein the electrically insulating filler structure comprises a second electrically insulating material different from the first electrically insulating material.