公开(公告)号：US20250104760A1

公开(公告)日：2025-03-27

申请号：US18471382

申请日：2023-09-21

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Sagar Suthram ,  Wilfred Gomes ,  Anand S. Murthy ,  Tahir Ghani ,  Pushkar Sharad Ranade

IPC: G11C11/4091 ,  G11C11/408 ,  G11C11/4094

Abstract: An IC device may include memory layers over a logic layer. A memory layer includes memory arrays, each of which includes memory cells arranged in rows and columns. A row of memory cells may be associated with a word line. A column of memory cells may be associated with a bit line. Bit lines of different memory arrays may be coupled using one or more vias or source/drain electrodes of transistors in the memory arrays. Alternatively, word lines of different memory arrays may be coupled using one or more vias or gate electrodes of transistors in the memory arrays. The logic layer has a logic circuit that can control data read operations and data write operations of the memory layers. The logic layer may include a power interconnect, which facilitates power delivery to the memory layers, and a signal interconnect, which facilitates signal transmission within the memory device.

公开(公告)号：US20250079399A1

公开(公告)日：2025-03-06

申请号：US18460918

申请日：2023-09-05

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Wilfred Gomes ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Nitin A. Deshpande ,  Pushkar Sharad Ranade ,  Abhishek A. Sharma

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498

Abstract: Embodiments of a microelectronic assembly may include a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including an active region including a capacitor; and a metallization stack including a first conductive trace electrically coupled to a first conductor of the capacitor and a second conductive trace electrically coupled to a second conductor of the capacitor, wherein the first conductive trace and the second conductive trace are parallel to the first and second surfaces and exposed at the third surface; and a second IC die including a fourth surface, where the first conductive trace and the second conductive trace at the third surface of the first IC die are electrically coupled to the fourth surface of the second IC die by interconnects.

公开(公告)号：US20250079263A1

公开(公告)日：2025-03-06

申请号：US18460931

申请日：2023-09-05

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Debendra Mallik ,  Wilfred Gomes ,  Pushkar Sharad Ranade ,  Nitin A. Deshpande ,  Ravindranath Vithal Mahajan ,  Abhishek A. Sharma

IPC: H01L23/473 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

Abstract: Embodiments of a microelectronic assembly may include a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including a substrate with a microchannel, and a metallization stack with a conductive trace that is parallel to the first and second surfaces and exposed at the third surface; and a second IC die having a fourth surface, wherein the conductive trace exposed at the third surface of the first IC die is electrically coupled to the fourth surface of the second IC die by an interconnect.

公开(公告)号：US20240222326A1

公开(公告)日：2024-07-04

申请号：US18148528

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Wilfred Gomes ,  Nisha Ananthakrishnan ,  Kemal Aygun ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Pushkar Sharad Ranade ,  Abhishek A. Sharma

IPC: H01L25/065 ,  H01L23/522 ,  H01L23/528 ,  H10B10/00 ,  H10B12/00 ,  H10B80/00

CPC classification number: H01L25/0655 ,  H01L23/5226 ,  H01L23/5283 ,  H10B10/12 ,  H10B12/37 ,  H10B80/00

Abstract: Embodiments of a microelectronic assembly include: a first integrated circuit (IC) die having a first memory circuit and a second memory circuit; a second IC die; a third IC die; and a package substrate. The first IC die is between the second IC die and the package substrate. The first IC die comprises: a first portion comprising a first active region and a first backend region in contact with the first active region; and a second portion comprising a second active region and a second backend region in contact with the second active region. The first memory circuit is in the first portion, the second memory circuit is in the second portion, the first active region comprises transistors that are larger than transistors in the second active region, and the first backend region comprises conductive traces that have a larger pitch than conductive traces in the second backend region.

公开(公告)号：US20240105860A1

公开(公告)日：2024-03-28

申请号：US17955235

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Tahir Ghani ,  WIlfred Gomes ,  Anand Murthy ,  Sagar Suthram ,  Pushkar Ranade

IPC: H01L29/93 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/93 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/66174

Abstract: An integrated circuit (IC) die includes a plurality of varactor devices, where at least one varactor of the plurality of varactor devices comprises a first electrode, a second electrode, and a multi-layer stack of ferroelectric material (e.g., ferroelectric variable capacitance material) disposed between the first and second electrodes. Other embodiments are disclosed and claimed.

公开(公告)号：US20240004129A1

公开(公告)日：2024-01-04

申请号：US17853732

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Debendra Mallik ,  John Heck ,  Pushkar Sharad Ranade ,  Ravindranath Vithal Mahajan ,  Thomas Liljeberg ,  Wilfred Gomes ,  Abhishek A. Sharma ,  Tahir Ghani

IPC: G02B6/12 ,  G02B6/13 ,  H01L25/16 ,  H01L23/00

CPC classification number: G02B6/12002 ,  G02B6/12004 ,  G02B6/13 ,  H01L25/167 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Embodiments of a microelectronic assembly comprise: a plurality of microelectronic sub-assemblies arranged in an array; and a plurality of photonic integrated circuit (PIC) dies, each PIC die having waveguides. Adjacent microelectronic sub-assemblies are coupled to one of the PIC dies by interconnects such that any one PIC die is coupled to more than two adjacent microelectronic sub-assemblies, and the microelectronic sub-assemblies coupled to each PIC die in the plurality of PIC dies are communicatively coupled by the waveguides in the PIC die. Each microelectronic sub-assembly comprises: an interposer integrated circuit (IC) die comprising one or more electrical controller circuit proximate to at least one edge of the interposer IC die; a first plurality of IC dies coupled to a first surface of the interposer IC die; and a second plurality of IC dies coupled to an opposing second surface of the interposer IC die.

公开(公告)号：US20230410907A1

公开(公告)日：2023-12-21

申请号：US18312867

申请日：2023-05-05

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Sagar Suthram ,  Tahir Ghani ,  Wilfred Gomes ,  Anand S. Murthy

IPC: G11C16/04 ,  H10B43/27 ,  G11C16/26 ,  G11C16/10 ,  H01L29/78 ,  H01L29/06 ,  H01L29/778 ,  H01L29/423 ,  H01L29/786

CPC classification number: G11C16/0483 ,  H10B43/27 ,  G11C16/26 ,  G11C16/10 ,  H01L29/78696 ,  H01L29/0665 ,  H01L29/778 ,  H01L29/42392 ,  H01L29/7851

Abstract: IC devices implementing 2T memory cells with angled transistors, and related assemblies and methods, are disclosed herein. A transistor is referred to as an “angled transistor” if a longitudinal axis of an elongated semiconductor structure of the transistor (e.g., a fin or a nanoribbon) is neither perpendicular nor parallel to any edges of front or back sides of a support structure (e.g., a die) over which the transistor is implemented. 2T memory cells with read and write transistors provided in different planes of an IC device, stacked substantially over one another, and having either the read transistors or the write transistors being angled transistors provide a promising way to increasing memory cell densities, drive current, and design flexibility in making electrical connections to, or between, various transistor terminals and control lines of memory arrays, thus providing good scalability in the number of 2T memory cells included in memory arrays.

公开(公告)号：US20230395676A1

公开(公告)日：2023-12-07

申请号：US17829706

申请日：2022-06-01

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Abhishek A. Sharma ,  Wilfred Gomes ,  Tahir Ghani ,  Anand S. Murthy ,  Pushkar Sharad Ranade

IPC: H01L29/423 ,  H01L29/06 ,  H01L27/092

CPC classification number: H01L29/4238 ,  H01L29/0665 ,  H01L29/42392 ,  H01L27/092

Abstract: IC devices with transistors having angled gates, and related assemblies and methods, are disclosed herein. A transistor is referred to as having an “angled gate” if an angle between a projection of the gate of the transistor onto a plane of a support structure (e.g., a die) over which the transistor is implemented and an analogous projection of a longitudinal axis of an elongated structure (e.g., a fin or a nanoribbon having one or more semiconductor materials) based on which the transistor is built is between 10 degrees and 80 degrees. Transistors having angled gates provide a promising way to increasing densities of transistors on the limited real estate of semiconductor chips and/or decreasing short-channel effects associated with continuous scaling of IC components.

公开(公告)号：US20230317140A1

公开(公告)日：2023-10-05

申请号：US17708448

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Sagar Suthram ,  Rajabali Koduri ,  Pushkar Ranade ,  Wilfred Gomes

IPC: G11C11/408 ,  G11C11/4094 ,  H03K19/17728 ,  H03K19/0185

CPC classification number: G11C11/4087 ,  G11C11/4094 ,  G11C11/4085 ,  H03K19/17728 ,  H03K19/018521

Abstract: In one embodiment, a memory comprises: a first subarray having a first plurality of memory cells, the first subarray having a first orientation; and a second subarray having a second plurality of memory cells, the second subarray having a second orientation, the second orientation orthogonal to the first orientation. Other embodiments are described and claimed.

公开(公告)号：US20230275067A1

公开(公告)日：2023-08-31

申请号：US17680368

申请日：2022-02-25

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Tahir Ghani ,  Anand S. Murthy ,  Wilfred Gomes ,  Sagar Suthram

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/38 ,  H01L23/473

CPC classification number: H01L25/0657 ,  H01L25/18 ,  H01L23/38 ,  H01L23/473 ,  H01L2225/06589

Abstract: Described herein are memory devices that include a cooling structure for cooling one or more memory arrays. The memory arrays may be static random access memory (SRAM) arrays formed in multiple layers as a stacked memory device. The cooling structure may cool one or more layers of an SRAM device. For example, a cooling structure may be formed around the SRAM device and coupled to a cooling device. Alternatively, a cooling layer may be included in a memory device and coupled to one or more thermal interface layers in thermal contact with a memory layer by cold vias. The cold vias transfer a cold temperature from the cooling layer to the thermal interface layer to cool the thermal interface layer and, in turn, the memory arrays.