公开(公告)号：US20210111066A1

公开(公告)日：2021-04-15

申请号：US16598058

申请日：2019-10-10

Applicant: International Business Machines Corporation

Inventor： Somnath Ghosh ,  Hsueh-Chung Chen ,  Yongan Xu ,  Yann Mignot ,  Lawrence A. Clevenger

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/311

Abstract: A method includes applying a first metallic layer having a first metallic material onto a substrate of a semiconductor component. The method further includes removing portions of the first metallic layer to form a first metallic line. The method further includes creating an opening in the first metallic line. The method also includes depositing a dielectric material on the substrate. The method further includes forming at least one trench in the dielectric material. The method also includes depositing a second metallic material within the at least one trench to form a second metallic line. At least the first and second metallic lines and the dielectric material form an interconnect structure of the semiconductor component.

公开(公告)号：US20240203780A1

公开(公告)日：2024-06-20

申请号：US18083380

申请日：2022-12-16

Applicant: International Business Machines Corporation

Inventor： Somnath Ghosh ,  Ruilong Xie ,  Stuart Sieg ,  Fee Li Lie ,  Kisik Choi

IPC: H01L21/683 ,  H01L23/544

CPC classification number: H01L21/6835 ,  H01L23/544 ,  H01L2221/68309 ,  H01L2221/68327 ,  H01L2223/54426

Abstract: A semiconductor structure includes a handler substrate and a device substrate bonded to the handler substrate. The handler substrate comprises a trench, and at least one alignment mark in a bottom surface of the trench. One or more dielectric layers are disposed in the trench and on the at least one alignment mark.

公开(公告)号：US20230411289A1

公开(公告)日：2023-12-21

申请号：US17664663

申请日：2022-05-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Kisik Choi ,  Junli Wang ,  Somnath Ghosh ,  Julien Frougier ,  Min Gyu Sung ,  Theodorus E. Standaert ,  Nicolas Jean Loubet ,  Huiming Bu

IPC: H01L23/528 ,  H01L23/48 ,  H01L23/535 ,  H01L29/06

CPC classification number: H01L23/5286 ,  H01L29/0665 ,  H01L23/535 ,  H01L23/481

Abstract: A first and a second source drain region, an upper source drain contact connected to the first source drain region, a bottom source drain contact connected to the second source drain region, a dielectric spacer surrounds opposite vertical side surfaces of the bottom source drain contact and overlaps a vertical side surface and a lower horizontal surface of a bottom isolation region. A width of the bottom source drain contact wider than a width of the second source drain. Forming an undoped silicon buffer epitaxy in an opening between and below a first and a second nanosheet stack, forming a contact to a first source drain adjacent to that, removing the undoped silicon buffer epitaxy below a second source drain between the first and the second nanosheet stack, forming a bottom contact to that, a width of the bottom contact is wider than a width of the second source drain.

公开(公告)号：US20230163029A1

公开(公告)日：2023-05-25

申请号：US17530971

申请日：2021-11-19

Applicant: International Business Machines Corporation

Inventor： Devika Sarkar Grant ,  Somnath Ghosh

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/02

CPC classification number: H01L21/76885 ,  H01L23/53266 ,  H01L21/02071 ,  H01L21/31111

Abstract: Structures in semiconductor devices, and methods for forming the structures, are described. In one embodiment, a hard mask layer of a deposition stack can be etched to pattern a hard mask. An interconnect layer of the deposition stack can be etched using the hard mask to pattern a plurality of metal lines. The hard mask can be removed. A liner layer of the deposition stack can be etched to remove a portion of the liner layer deposited directly on a dielectric layer of the deposition stack. In response to etching the liner layer, a remaining portion of the liner layer can be deposited between the metal lines and the dielectric layer.

公开(公告)号：US20230154783A1

公开(公告)日：2023-05-18

申请号：US17527229

申请日：2021-11-16

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Stuart Sieg ,  Somnath Ghosh ,  Kisik Choi ,  Kevin Shawn Petrarca

IPC: H01L21/74 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/528 ,  H01L23/535 ,  H01L27/088

CPC classification number: H01L21/743 ,  H01L21/76879 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/535 ,  H01L23/5286 ,  H01L27/0886

Abstract: Embodiments disclosed herein describe a semiconductor structure. The semiconductor structure may include a device region with a first source/drain (S/D) and a second S/D. The semiconductor structure may also include a buried power rail (BPR) under the device region. A critical dimension of the BPR may be larger than a distance between the first S/D and the second S/D. The semiconductor structure may also include a via-contact-to-buried power rail (VBPR) between the BPR and the S/D.

公开(公告)号：US20230100113A1

公开(公告)日：2023-03-30

申请号：US17488389

申请日：2021-09-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Stuart Sieg ,  Somnath Ghosh ,  Kisik Choi ,  Rishikesh Krishnan ,  Alexander Reznicek

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L21/311

Abstract: Integrated chips and methods of forming the same include forming a stack of layers, including a device stack above a first sacrificial layer, above a substrate. The first sacrificial layer is replaced with a first etch stop layer. The substrate is removed, exposing a substrate-side of the stack of layers. The substrate-side of the stack of layers is etched to form a trench, stopping on the first etch stop layer. A conductive line is formed in the trench.

公开(公告)号：US20220189826A1

公开(公告)日：2022-06-16

申请号：US17687806

申请日：2022-03-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chanro Park ,  Kenneth Chun Kuen Cheng ,  Koichi Motoyama ,  Brent Anderson ,  Somnath Ghosh

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/3213

Abstract: A method is presented for back-end-of-the-line (BEOL) metallization with lines formed by subtractive patterning and vias formed by damascene processes. The method includes depositing a dielectric layer over a conductive layer formed over a substrate, forming spacers surrounding mandrel sections formed over the dielectric layer, selectively depositing gap fill material adjacent the spacers, selectively removing the spacers, etching the dielectric layer and the conductive layer to expose a top surface of the substrate, depositing and planarizing an inter-layer dielectric, selectively forming openings in the dielectric layer, and filling the openings with a conductive material to define metal vias.

公开(公告)号：US11302571B2

公开(公告)日：2022-04-12

申请号：US16598058

申请日：2019-10-10

Applicant: International Business Machines Corporation

Inventor： Somnath Ghosh ,  Hsueh-Chung Chen ,  Yongan Xu, Jr. ,  Yann Mignot ,  Lawrence A. Clevenger

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/311

Abstract: A method includes applying a first metallic layer having a first metallic material onto a substrate of a semiconductor component. The method further includes removing portions of the first metallic layer to form a first metallic line. The method further includes creating an opening in the first metallic line. The method also includes depositing a dielectric material on the substrate. The method further includes forming at least one trench in the dielectric material. The method also includes depositing a second metallic material within the at least one trench to form a second metallic line. At least the first and second metallic lines and the dielectric material form an interconnect structure of the semiconductor component.

公开(公告)号：US11244897B2

公开(公告)日：2022-02-08

申请号：US16840506

申请日：2020-04-06

Applicant: International Business Machines Corporation

Inventor： Chanro Park ,  Koichi Motoyama ,  Kenneth Chun Kuen Cheng ,  Somnath Ghosh ,  Chih-Chao Yang

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528 ,  H01L21/033

Abstract: Interconnect structures and methods for forming the interconnect structures generally include a subtractive etching process to form a fully aligned top via and metal line interconnect structure. The interconnect structure includes a top via and a metal line formed of an alternative metal other than copper or tungsten. A conductive etch stop layer is intermediate the top via and the metal line. The top via is fully aligned to the metal line.

公开(公告)号：US10998193B1

公开(公告)日：2021-05-04

申请号：US16748898

申请日：2020-01-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Timothy Mathew Philip ,  Somnath Ghosh ,  Daniel James Dechene ,  Robert Robison ,  Lawrence A. Clevenger

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/02 ,  H01L21/027 ,  H01L21/306 ,  H01L21/3213

Abstract: Integrated chips and methods of forming the same include forming a first set of sidewall spacers on a first mandrel at first vertical level. The first mandrel is etched away. A second set of sidewall spacers is formed on a second mandrel at a second vertical level. A portion of the second set of sidewall spacers vertically overlaps with a portion of the first set of sidewall spacers. The second mandrel is etched away. A first hardmask layer is etched, using the vertically overlapping first set of sidewall spacers and second set of sidewall spacers as a mask.