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    PROOF MASS AND POLYSILICON ELECTRODE INTEGRATED THEREON
    11.
    发明申请
    PROOF MASS AND POLYSILICON ELECTRODE INTEGRATED THEREON 审中-公开

    公开(公告)号：US20190035905A1

    公开(公告)日：2019-01-31

    申请号：US16044233

    申请日：2018-07-24

    Applicant: InvenSense, Inc.

    Inventor： Bongsang KIM ,  Jongwoo SHIN ,  Joseph SEEGER ,  Logeeswaran Veerayah JAYARAMAN ,  Houri JOHARI-GALLE

    IPC: H01L29/49 ,  G01P15/097 ,  H01L23/532

    Abstract: A method includes depositing a silicon layer over a first oxide layer that overlays a first silicon substrate. The method further includes depositing a second oxide layer over the silicon layer to form a composite substrate. The composite substrate is bonded to a second silicon substrate to form a micro-electro-mechanical system (MEMS) substrate. Holes within the second silicon substrate are formed by reaching the second oxide layer of the composite substrate. The method further includes removing a portion of the second oxide layer through the holes to release MEMS features. The MEMS substrate may be bonded to a CMOS substrate.

    CMOS-MEMS INTEGRATION USING METAL SILICIDE FORMATION
    13.
    发明申请
    CMOS-MEMS INTEGRATION USING METAL SILICIDE FORMATION 有权
    使用金属硅化物形成的CMOS-MEMS集成

    公开(公告)号：US20170057813A1

    公开(公告)日：2017-03-02

    申请号：US14838237

    申请日：2015-08-27

    Applicant: InvenSense, Inc.

    Inventor： Jong Il SHIN ,  Peter SMEYS ,  Jongwoo SHIN

    IPC: B81C1/00 ,  B81B7/00

    CPC classification number: B81C1/00238 ,  B81B7/0006 ,  B81B2207/012 ,  B81C2203/019 ,  B81C2203/036 ,  B81C2203/0792

    Abstract: A method and system for forming a MEMS device are disclosed. In a first aspect, the method comprises providing a conductive material over at least a portion of a top metal layer of a base substrate, patterning the conductive material and the at least a portion of the top metal layer, and bonding the conductive material with a device layer of a MEMS substrate via metal silicide formation. In a second aspect, the MEMS device comprises a MEMS substrate, wherein the MEMS substrate includes a handle layer, a device layer, and an insulating layer in between. The MEMS device further comprises a base substrate, wherein the base substrate includes a top metal layer and a conductive material over at least a portion of the top metal layer, wherein the conductive material is bonded with the device layer via metal silicide formation.

    Abstract translation: 公开了一种用于形成MEMS器件的方法和系统。 在第一方面，该方法包括在基底衬底的顶部金属层的至少一部分上提供导电材料，图案化导电材料和顶部金属层的至少一部分，以及将导电材料与 通过金属硅化物形成MEMS衬底的器件层。 在第二方面，MEMS器件包括MEMS衬底，其中MEMS衬底包括手柄层，器件层和其间的绝缘层。 MEMS器件还包括基底，其中基底衬底包括在顶部金属层的至少一部分上的顶部金属层和导电材料，其中导电材料通过金属硅化物形成与器件层结合。

    METHOD OF INCREASING MEMS ENCLOSURE PRESSURE USING OUTGASSING MATERIAL
    14.
    发明申请
    METHOD OF INCREASING MEMS ENCLOSURE PRESSURE USING OUTGASSING MATERIAL 有权
    使用外加材料增加MEMS外壳压力的方法

    公开(公告)号：US20170001861A1

    公开(公告)日：2017-01-05

    申请号：US15265668

    申请日：2016-09-14

    Applicant: InvenSense, Inc.

    Inventor： Cerina ZHANG ,  Martin LIM ,  Jongwoo SHIN ,  Joseph SEEGER

    IPC: B81C1/00 ,  B81B7/00

    CPC classification number: B81C1/00301 ,  B81B7/007 ,  B81B7/02 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81C1/0023 ,  B81C1/00238 ,  B81C1/00246 ,  B81C1/00269 ,  B81C2201/0104 ,  B81C2201/0132 ,  B81C2203/0145 ,  B81C2203/019 ,  B81C2203/035 ,  B81C2203/0792

    Abstract: Semiconductor manufacturing processes include providing a first substrate having a first passivation layer disposed above a patterned top-level metal layer, and further having a second passivation layer disposed over the first passivation layer; the second passivation layer has a top surface. The processes further include forming an opening in a first portion of the second passivation layer, and the opening exposes a portion of a surface of the first passivation layer. The processes further include patterning the second and first passivation layers to expose portions of the patterned top-level metal layer and bonding a second substrate and the first substrate to each other. The bonding occurs within a temperature range in which at least the exposed portion of the first passivation layer undergoes outgassing.

    Abstract translation: 半导体制造工艺包括提供第一衬底，其具有设置在图案化顶层金属层上方的第一钝化层，并且还具有设置在第一钝化层上的第二钝化层; 第二钝化层具有顶表面。 所述方法还包括在第二钝化层的第一部分中形成开口，并且开口暴露第一钝化层的表面的一部分。 所述方法还包括图案化第二钝化层和第一钝化层以暴露图案化顶层金属层的部分并将第二基板和第一基板彼此接合。 接合发生在至少第一钝化层的暴露部分经历脱气的温度范围内。

    CMOS-MEMS INTEGRATED DEVICE INCLUDING MULTIPLE CAVITIES AT DIFFERENT CONTROLLED PRESSURES AND METHODS OF MANUFACTURE
    16.
    发明申请
    CMOS-MEMS INTEGRATED DEVICE INCLUDING MULTIPLE CAVITIES AT DIFFERENT CONTROLLED PRESSURES AND METHODS OF MANUFACTURE 有权
    CMOS-MEMS集成器件，其中包括在不同的控制压力下的多个CAVIITY和制造方法

    公开(公告)号：US20150129991A1

    公开(公告)日：2015-05-14

    申请号：US14603185

    申请日：2015-01-22

    Applicant: InvenSense, Inc.

    Inventor： Daesung LEE ,  Jongwoo SHIN ,  Jong Il SHIN ,  Peter SMEYS ,  Martin LIM

    IPC: B81C1/00 ,  B81B7/00

    CPC classification number: B81C1/0023 ,  B81B7/0038 ,  B81B7/0041 ,  B81B7/02 ,  B81B2201/0228 ,  B81B2207/017 ,  B81C1/00285 ,  B81C2203/019 ,  B81C2203/035 ,  B81C2203/0785

    Abstract: An integrated MEMS device comprises two substrates where the first and second substrates are coupled together and have two enclosures there between. One of the first and second substrates includes an outgassing source layer and an outgassing barrier layer to adjust pressure within the two enclosures. The method includes depositing and patterning an outgassing source layer and a first outgassing barrier layer on the substrate, resulting in two cross-sections. In one of the two cross-sections a top surface of the outgassing source layer is not covered by the outgassing barrier layer and in the other of the two cross-sections the outgassing source layer is encapsulated in the outgassing barrier layer. The method also includes depositing conformally a second outgassing barrier layer and etching the second outgassing barrier layer such that a spacer of the second outgassing barrier layer is left on sidewalls of the outgassing source layer.

    Abstract translation: 集成MEMS器件包括两个基板，其中第一和第二基板耦合在一起并且其间具有两个外壳。 第一和第二基板之一包括除气源层和去气阻挡层，以调节两个外壳内的压力。 该方法包括在基板上沉积和图案化除气源层和第一除气阻挡层，产生两个横截面。 在两个横截面之一中，除气源层的顶表面不被除气阻挡层覆盖，而在两个横截面中的另一个中，除气源层被封装在除气阻挡层中。 该方法还包括平行地沉积第二除气阻挡层并蚀刻第二除气阻挡层，使得第二除气阻挡层的间隔物留在除气源层的侧壁上。

    INTERNAL ELECTRICAL CONTACT FOR ENCLOSED MEMS DEVICES
    17.
    发明申请
    INTERNAL ELECTRICAL CONTACT FOR ENCLOSED MEMS DEVICES 有权
    用于封装的MEMS器件的内部电气接点

    公开(公告)号：US20140349434A1

    公开(公告)日：2014-11-27

    申请号：US14456973

    申请日：2014-08-11

    Applicant: InvenSense, Inc.

    Inventor： Kegang HUANG ,  Jongwoo SHIN ,  Martin LIM ,  Michael Julian DANEMAN ,  Joseph SEEGER

    IPC: B81C1/00

    CPC classification number: B81C1/00301 ,  B81B7/0064 ,  B81B2207/098 ,  B81C1/00269 ,  B81C2203/0118 ,  B81C2203/019 ,  B81C2203/031

    Abstract: A method of fabricating electrical connections in an integrated MEMS device is disclosed. The method comprises forming a MEMS wafer. Forming a MEMS wafer includes forming one cavity in a first semiconductor layer, bonding the first semiconductor layer to a second semiconductor layer with a dielectric layer disposed between the first semiconductor layer and the second semiconductor layer, and etching at least one via through the second semiconductor layer and the dielectric layer and depositing a conductive material on the second semiconductor layer and filling the at least one via. Forming a MEMS wafer also includes patterning and etching the conductive material to form one standoff and depositing a germanium layer on the conductive material, patterning and etching the germanium layer, and patterning and etching the second semiconductor layer to define one MEMS structure. The method also includes bonding the MEMS wafer to a base substrate.

    Abstract translation: 公开了一种在集成MEMS器件中制造电连接的方法。 该方法包括形成MEMS晶片。 形成MEMS晶片包括在第一半导体层中形成一个空腔，将第一半导体层与设置在第一半导体层和第二半导体层之间的电介质层结合到第二半导体层，并且通过第二半导体蚀刻至少一个通孔 层和介电层，并在第二半导体层上沉积导电材料并填充至少一个通孔。 形成MEMS晶片还包括图案化和蚀刻导电材料以形成一个间隔并在导电材料上沉积锗层，图案化和蚀刻锗层，以及图案化和蚀刻第二半导体层以限定一个MEMS结构。 该方法还包括将MEMS晶片接合到基底基板。

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