利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

19 条记录 (耗时 0.016 秒)

    SEMICONDUCTOR DEVICE HAVING INTERCONNECTION STRUCTURE
    11.
    发明申请
    SEMICONDUCTOR DEVICE HAVING INTERCONNECTION STRUCTURE 有权
    具有互连结构的半导体器件

    公开(公告)号：US20170011996A1

    公开(公告)日：2017-01-12

    申请号：US15201922

    申请日：2016-07-05

    申请人： Dohyun LEE ,  Youngwoo Park ,  Junghoon Park ,  Jaeduk Lee

    发明人： Dohyun LEE ,  Youngwoo Park ,  Junghoon Park ,  Jaeduk Lee

    IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L27/115

    CPC分类号： H01L21/76877 ,  H01L21/76816 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53266 ,  H01L23/53295 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

    摘要： A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure. The upper interconnection structure includes an upper interconnection and an upper barrier layer. The lower interconnection structure includes a lower interconnection and a lower barrier layer. The upper barrier layer is under a bottom surface of the upper interconnection and does not cover side surfaces of the upper interconnection. The lower barrier layer is under a bottom surface of the lower interconnection and covers side surfaces of the lower interconnection.

    摘要翻译： 半导体器件包括在半导体衬底上的半导体图案，半导体图案上的三维存储器阵列以及半导体图案和半导体衬底之间的外围互连结构。 外围互连结构包括在较低互连结构上的上互连结构。 上互连结构包括上互连和上阻挡层。 下部互连结构包括下部互连和下部阻挡层。 上阻挡层在上互连的底表面下方并且不覆盖上互连的侧表面。 下阻挡层在下互连的底表面下方并且覆盖下互连的侧表面。

    Semiconductor devices including word line interconnecting structures
    12.
    发明授权
    Semiconductor devices including word line interconnecting structures 有权
    半导体器件包括字线互连结构

    公开(公告)号：US09337207B2

    公开(公告)日：2016-05-10

    申请号：US14191542

    申请日：2014-02-27

    申请人： Jintaek Park ,  Youngwoo Park ,  Jaeduk Lee

    发明人： Jintaek Park ,  Youngwoo Park ,  Jaeduk Lee

    IPC分类号： H01L29/76 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/11556 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

    摘要： A semiconductor memory device includes a substrate including a cell region and an interconnection region, adjacent first and second rows of vertical channels extending vertically from the substrate in the cell region, and layers of word lines stacked on the substrate. Each layer includes a first word line through which the first row of vertical channels passes and a second word line through which the second row of vertical channels passes, and the word lines include respective word line pads extending into the interconnection region. An isolation pattern separates the first and second word lines in the cell region and the interconnection region. First and second pluralities of contact plugs are disposed on opposite sides of the isolation pattern in the interconnection region and contact the word line pads.

    摘要翻译： 半导体存储器件包括：衬底，其包括单元区域和互连区域;相邻的从单元区域中的衬底垂直延伸的第一和第二排垂直沟道以及堆叠在衬底上的字线层。 每层包括第一行垂直通道通过的第一字线和第二行垂直通道通过的第二字线，并且字线包括延伸到互连区域中的相应字线焊盘。 隔离图案分离单元区域和互连区域中的第一和第二字线。 第一和第二多个接触插塞设置在互连区域中的隔离图案的相对侧上，并与字线焊盘接触。

    Three-dimensional semiconductor devices and methods of fabricating the same
    14.
    发明授权
    Three-dimensional semiconductor devices and methods of fabricating the same 有权
    三维半导体器件及其制造方法

    公开(公告)号：US09019739B2

    公开(公告)日：2015-04-28

    申请号：US14152440

    申请日：2014-01-10

    申请人： Jintaek Park ,  Kohji Kanamori ,  Youngwoo Park ,  Jaeduk Lee

    发明人： Jintaek Park ,  Kohji Kanamori ,  Youngwoo Park ,  Jaeduk Lee

    IPC分类号： G11C5/02 ,  H01L27/115 ,  G11C7/02 ,  G11C7/18 ,  G11C7/10

    CPC分类号： G11C5/025 ,  G11C7/02 ,  G11C7/1039 ,  G11C7/18 ,  H01L27/11573 ,  H01L27/11582

    摘要： According to example embodiments of inventive concepts, a three-dimensional semiconductor device may include: a memory cell array including memory cells that may be arranged three-dimensionally, the memory cell array including a left side opposite a right side, and a top side opposite a bottom side in a plan view; at least one word line decoder adjacent to at least one of the left and right sides of the memory cell array; a page buffer adjacent to the bottom side of the memory cell array; and a string selection line decoder adjacent to one of the top and bottom sides of the memory cell array.

    摘要翻译： 根据本发明构思的示例性实施例，三维半导体器件可以包括：存储单元阵列，其包括可以三维布置的存储器单元，所述存储单元阵列包括与右侧相对的左侧， 平面图的底面; 与存储单元阵列的左侧和右侧中的至少一个相邻的至少一个字线解码器; 邻近存储单元阵列的底侧的页缓冲器; 以及与存储单元阵列的顶侧和底侧之一相邻的串选择线解码器。

    THREE-DIMENSIONAL SEMICONDUCTOR DEVICES WITH CURRENT PATH SELECTION STRUCTURE AND METHODS OF OPERATING THE SAME
    15.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR DEVICES WITH CURRENT PATH SELECTION STRUCTURE AND METHODS OF OPERATING THE SAME 有权
    具有电流路径选择结构的三维半导体器件及其操作方法

    公开(公告)号：US20140197469A1

    公开(公告)日：2014-07-17

    申请号：US14150452

    申请日：2014-01-08

    申请人： Jaeduk Lee ,  Youngwoo Park ,  Jintaek Park ,  Dohyun Lee ,  Kohji Kanamori

    发明人： Jaeduk Lee ,  Youngwoo Park ,  Jintaek Park ,  Dohyun Lee ,  Kohji Kanamori

    IPC分类号： H01L27/105

    CPC分类号： H01L27/1052 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11524 ,  H01L27/11556

    摘要： Provided are three-dimensional semiconductor devices and methods of operating the same. The three-dimensional semiconductor devices may include active patterns arranged on a substrate to have a multi-layered and multi-column structure and drain patterns connected to respective columns of the active patterns. The methods may include a layer-selection step connecting a selected one of layers of the active patterns selectively to the drain patterns. For example, the layer-selection step may be performed in such a way that widths of depletion regions to be formed in end-portions of the active patterns are differently controlled depending on to a height from the substrate.

    摘要翻译： 提供三维半导体器件及其操作方法。 三维半导体器件可以包括布置在衬底上的有源图案，以具有连接到有源图案的相应列的多层和多列结构以及漏极图案。 所述方法可以包括选择性地将有源图案的层中所选择的一个层连接到漏极图案的层选择步骤。 例如，层选择步骤可以以这样的方式执行，使得在有源图案的端部中形成的耗尽区的宽度根据与基板的高度不同地被控制。

    Non-volatile memory devices and methods of manufacturing the same
    16.
    发明授权
    Non-volatile memory devices and methods of manufacturing the same 有权
    非易失性存储器件及其制造方法

    公开(公告)号：US08368138B2

    公开(公告)日：2013-02-05

    申请号：US12884668

    申请日：2010-09-17

    申请人： Yong-Lack Choi ,  Sunghoi Hur ,  Jaeduk Lee ,  Jungdal Choi

    发明人： Yong-Lack Choi ,  Sunghoi Hur ,  Jaeduk Lee ,  Jungdal Choi

    IPC分类号： H01L29/788

    CPC分类号： H01L29/7883 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42336

    摘要： Semiconductor devices and methods of forming the same. The semiconductor devices include a tunnel insulation layer on a substrate, a floating gate on the tunnel insulation layer, a gate insulation layer on the floating gate, a low-dielectric constant (low-k) region between the top of the floating gate and the gate insulation layer, the low-k region having a lower dielectric constant than a silicon oxide, and a control gate on the gate insulation layer.

    摘要翻译： 半导体器件及其形成方法。 半导体器件包括在衬底上的隧道绝缘层，隧道绝缘层上的浮动栅极，浮置栅极上的栅极绝缘层，浮动栅极的顶部和第二栅极之间的低介电常数（低k）区域 栅极绝缘层，具有比氧化硅更低的介电常数的低k区域以及栅极绝缘层上的控制栅极。

    Non-Volatile Memory Devices Having Reduced Susceptibility to Leakage of Stored Charges and Methods of Forming Same
    17.
    发明申请
    Non-Volatile Memory Devices Having Reduced Susceptibility to Leakage of Stored Charges and Methods of Forming Same 审中-公开
    具有降低存储容量泄漏的易感性的非易失性存储器件及其形成方法

    公开(公告)号：US20110079839A1

    公开(公告)日：2011-04-07

    申请号：US12894863

    申请日：2010-09-30

    申请人： Fayrushin Albert ,  Kwang Soo Seol ,  Jaeduk Lee

    发明人： Fayrushin Albert ,  Kwang Soo Seol ,  Jaeduk Lee

    IPC分类号： H01L29/788

    CPC分类号： H01L29/4234 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/792

    摘要： Provided is a semiconductor device. The semiconductor device includes a substrate, a tunnel insulating layer, a charge storage pattern, a blocking layer, a gate electrode. The tunnel insulating layer is disposed over the substrate. The charge storage pattern is disposed over the tunnel insulating layer. The charge storage pattern has an upper surface, a sidewall, and an edge portion between the upper surface and the sidewall. The blocking layer includes an insulating pattern covering the edge portion of the charge storage pattern, and a gate dielectric layer covering the upper surface, the sidewall, and the edge portion of the charge storage pattern. The gate electrode is disposed over the blocking layer, the gate electrode covering the upper surface, the sidewall, and the edge portion of the charge storage pattern.

    摘要翻译： 提供一种半导体器件。 半导体器件包括衬底，隧道绝缘层，电荷存储图案，阻挡层，栅电极。 隧道绝缘层设置在衬底上。 电荷存储图案设置在隧道绝缘层上。 电荷存储图案具有在上表面和侧壁之间的上表面，侧壁和边缘部分。 阻挡层包括覆盖电荷存储图案的边缘部分的绝缘图案，以及覆盖电荷存储图案的上表面，侧壁和边缘部分的栅极电介质层。 栅电极设置在阻挡层上，栅电极覆盖电荷存储图案的上表面，侧壁和边缘部分。

    Non-Volatile Memory Devices Having Semiconductor Barrier Patterns and Methods of Forming Such Devices
    19.
    发明申请
    Non-Volatile Memory Devices Having Semiconductor Barrier Patterns and Methods of Forming Such Devices 审中-公开
    具有半导体阻挡图案的非易失性存储器件和形成这种器件的方法

    公开(公告)号：US20110073928A1

    公开(公告)日：2011-03-31

    申请号：US12894844

    申请日：2010-09-30

    申请人： ByungKyu Cho ,  Sunghoi Hur ,  Jaeduk Lee ,  Jungdal Choi

    发明人： ByungKyu Cho ,  Sunghoi Hur ,  Jaeduk Lee ,  Jungdal Choi

    IPC分类号： H01L29/788

    CPC分类号： H01L29/42324 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/7881

    摘要： Provided are a non-volatile memory device and a method of forming the same. The non-volatile memory device includes: a tunnel insulation layer on a substrate; a floating gate on the tunnel insulation layer; a blocking insulation layer on the floating gate; a first barrier pattern, between the top of the floating gate and the blocking insulation layer, having a higher conduction band energy level than the floating gate; and a control gate on the blocking insulation layer.

    摘要翻译： 提供一种非易失性存储器件及其形成方法。 非易失性存储器件包括：衬底上的隧道绝缘层; 隧道绝缘层上的浮栅; 浮栅上的阻挡绝缘层; 在浮置栅极的顶部和阻挡绝缘层之间的第一阻挡图案具有比浮动栅极更高的导带能级; 和阻挡绝缘层上的控制栅极。