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    Magnetoresistive element and memory circuit including a free layer
    11.
    发明授权
    Magnetoresistive element and memory circuit including a free layer 有权

    公开(公告)号：US10304508B2

    公开(公告)日：2019-05-28

    申请号：US15578377

    申请日：2016-05-31

    Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY

    Inventor： Satoshi Sugahara ,  Yota Takamura ,  Shigeki Nakagawa

    IPC: G11C11/16 ,  H01L43/08 ,  H01L27/105 ,  H01L29/82 ,  H01L41/09 ,  G11C11/14 ,  H01L27/22

    Abstract: A magnetoresistive element includes: a free layer that includes a magnetostrictive layer containing a magnetostrictive material; a pin layer that includes a first ferromagnetic layer; a thin film that is located between the pin layer and the free layer; a piezoelectric substance that is located so as to surround at least a part of the magnetostrictive layer from a direction intersecting with a stacking direction of the free layer and the pin layer and applies a pressure to the magnetostrictive layer; and an electrode that is capable of applying a voltage different from a voltage applied to the free layer and a voltage applied to the pin layer and applies a voltage to the piezoelectric substance so that the piezoelectric substance applies a pressure to the magnetostrictive layer.

    Memory circuit with a bistable circuit and a non-volatile element
    12.
    发明授权
    Memory circuit with a bistable circuit and a non-volatile element 有权

    公开(公告)号：US10049740B2

    公开(公告)日：2018-08-14

    申请号：US15501247

    申请日：2015-08-06

    Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY ,  KANAGAWA ACADEMY OF SCIENCE AND TECHNOLOGY

    Inventor： Satoshi Sugahara ,  Yusuke Shuto ,  Shuichiro Yamamoto

    IPC: G11C11/00 ,  G11C14/00 ,  G11C11/419 ,  G11C11/16

    Abstract: A memory circuit includes: cells arranged in rows and columns so that the rows are grouped to form banks each including one or more rows, each cell including: a bistable circuit storing data; and a non-volatile element storing data stored in the bistable circuit in a non-volatile manner and restoring data stored in a non-volatile manner to the bistable circuit; and a controller that performs a store operation on each row in turn; sets a voltage supplied, as a power-supply voltage, to cells in a first bank, which includes a row on which the store operation is performed, of the banks to a first voltage; and sets a voltage supplied, as a power-supply voltage, to cells in a bank of the banks other than the first bank to a second voltage that is less than the first voltage but at which data in the bistable circuit is retained.

    ELECTRONIC CIRCUIT
    15.
    发明申请
    ELECTRONIC CIRCUIT 有权

    公开(公告)号：US20250046365A1

    公开(公告)日：2025-02-06

    申请号：US18926916

    申请日：2024-10-25

    Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY

    Inventor： Satoshi Sugahara ,  Daiki Kitagata ,  Shuichiro Yamamoto

    IPC: G11C11/412 ,  G11C11/418 ,  G11C11/419 ,  G11C11/56 ,  G11C14/00 ,  H03K3/356

    Abstract: An electronic circuit includes a cell array including memory cells each including a bistable circuit that includes first and second inverter circuits, each having a first mode characterized by there being substantially no hysteresis in transfer characteristics and a second mode characterized by there being hysteresis in the transfer characteristics, and being switchable between the first and second modes, and a control circuit configured to, after powering off a first memory cell that store data that are not required to be retained, put the bistable circuit in a remaining second memory cell into the second mode, and supply a second power supply voltage that allows the bistable circuit in the second mode to retain data and is lower than a first power supply voltage supplied to the bistable circuit when data is read and/or written, to the bistable circuit in the second memory cell while maintaining the second mode.

    Thermoelectric conversion device
    16.
    发明授权
    Thermoelectric conversion device 有权

    公开(公告)号：US12185628B2

    公开(公告)日：2024-12-31

    申请号：US18276326

    申请日：2022-02-15

    Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY

    Inventor： Satoshi Sugahara ,  Hayato Kumagai

    IPC: H10N10/17 ,  H10N10/82

    Abstract: A thermoelectric conversion device includes thermoelectric layers and connection layers that are alternately provided in a first direction parallel to surfaces of the thermoelectric layers, and are connected to each other, thermally conductive layers that are connected to the respective connection layers, and extends in a second direction intersecting the surfaces, a first insulating layer that has a smaller thermal conductivity than the thermally conductive layers, and a second insulating layer that has a smaller thermal conductivity than the first insulating layer, is provided between the first insulating layer and the thermoelectric layers, and has a thickness equal to or greater than ¼ of a distance between an end of the thermally conductive layer at a side of one of the thermoelectric layers and a center of another of the connection layers in the first direction, the thermally conductive layers penetrating through the first and second insulating layers.

    BISTABLE CIRCUIT AND ELECTRONIC CIRCUIT
    17.
    发明申请
    BISTABLE CIRCUIT AND ELECTRONIC CIRCUIT 有权

    公开(公告)号：US20220406370A1

    公开(公告)日：2022-12-22

    申请号：US17877452

    申请日：2022-07-29

    Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY

    Inventor： Satoshi Sugahara ,  Yusaku Shiotsu

    IPC: G11C11/412 ,  G11C11/419 ,  H03K3/3565 ,  H01L27/11

    Abstract: A bistable circuit includes a pair of inverter circuits each including a first FET being connected between a power supply line and an intermediate node and having a gate coupled to an input node and a first conductivity type channel, a second FET being connected between the intermediate node and an output node and having a gate coupled to the input node and the first conductivity type channel, a third FET being connected between the intermediate node and a bias node, a fourth FET being connected between the output node and a control line and having a gate coupled to a word line and a second conductivity type channel, wherein the pair of inverter circuits are connected in a loop shape, and gates of the third FETs of the pair of inverter circuits are coupled to one of the input and output nodes of the pair of inverter circuits.

    ELECTRONIC CIRCUIT
    18.
    发明申请
    ELECTRONIC CIRCUIT 审中-公开

    公开(公告)号：US20180069534A1

    公开(公告)日：2018-03-08

    申请号：US15558059

    申请日：2016-03-24

    Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY

    Inventor： Satoshi Sugahara ,  Shuichiro Yamamoto

    IPC: H03K3/3565 ,  G11C11/413 ,  G11C11/412 ,  H02M7/42

    CPC classification number: H03K3/3565 ,  G11C5/148 ,  G11C11/412 ,  G11C11/413 ,  G11C14/0054 ,  H02M7/42 ,  H03K3/02337 ,  H03K3/356

    Abstract: An electronic circuit includes: a bistable circuit connected between first and second power sources respectively supplied with first and second power-supply voltages and including first and second inverters connected in a loop being inverter circuits switching between first and second modes; a control circuit outputting first and second signals respectively setting the inverter circuits in the first and second modes to the inverter circuits; and a power-supply circuit supplying a first voltage as a power-supply voltage while the inverter circuits are in the first mode, and supplying a second voltage higher than the first voltage as the power-supply voltage while the inverter circuits are in the second mode, wherein the first mode exhibits hysteresis in a transfer characteristic curve and the second mode exhibits no hysteresis in a transfer characteristic curve, and/or the first mode has a steeper transfer characteristic curve than the second mode.

    MEMORY CIRCUIT PROVIDED WITH BISTABLE CIRCUIT AND NON-VOLATILE ELEMENT
    20.
    发明申请
    MEMORY CIRCUIT PROVIDED WITH BISTABLE CIRCUIT AND NON-VOLATILE ELEMENT 有权
    具有双向电路和非易失性元件的存储器电路

    公开(公告)号：US20150070974A1

    公开(公告)日：2015-03-12

    申请号：US14543487

    申请日：2014-11-17

    Applicant: Japan Science and Technology Agency

    Inventor： Yusuke Shuto ,  Shuichiro Yamamoto ,  Satoshi Sugahara

    IPC: G11C14/00

    CPC classification number: G11C14/0081 ,  G11C11/1675 ,  G11C11/1693

    Abstract: A memory circuit includes: a bistable circuit (30) that stores data; nonvolatile elements (MTJ1, MTJ2) that store data written in the bistable circuit in a nonvolatile manner, and restore data stored in a nonvolatile manner into the bistable circuit; and a control unit that stores data written in the bistable circuit in a nonvolatile manner and cuts off a power supply to the bistable circuit when the period not to read data from or write data into the bistable circuit is longer than a predetermined time period, and does not store data written in the bistable circuit in a nonvolatile manner and makes the supply voltage for the bistable circuit lower than a voltage during the period to read data from or write data into the bistable circuit when the period not to read or write data is shorter than the predetermined time period.

    Abstract translation: 存储电路包括：存储数据的双稳态电路（30）; 以非挥发性方式存储写在双稳态电路中的数据的非易失性元件（MTJ1，MTJ2），将以非易失性方式存储的数据恢复到双稳态电路中; 以及控制单元，其以非易失性方式存储写入双稳态电路中的数据，并且当不从双稳态电路读取数据或将数据写入双稳态电路的时间长于预定时间段时，切断对双稳态电路的电源，并且 不以非易失性方式存储写入双稳态电路中的数据，并且当不读或写数据的周期是双稳态电路的电源电压低于该周期期间的电压以从数据读取数据或将数据写入双稳态电路 比预定时间段短。

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