公开(公告)号：US20120070972A1

公开(公告)日：2012-03-22

申请号：US12884500

申请日：2010-09-17

Applicant: Neng-Kuo Chen ,  Jeff J. Xu

Inventor： Neng-Kuo Chen ,  Jeff J. Xu

IPC: H01L21/3205

CPC classification number: H01L21/02337 ,  H01L21/28123 ,  H01L21/31116 ,  H01L21/32115 ,  H01L21/32137

Abstract: Provided is a method of planarizing a semiconductor device. The method includes providing a substrate. The method includes forming a first layer over the substrate. The method includes forming a second layer over the first layer. The first and second layers have different material compositions. The method includes forming a third layer over the second layer. The method includes performing a polishing process on the third layer until the third layer is substantially removed. The method includes performing an etch back process to remove the second layer and a portion of the first layer. Wherein an etching selectivity of the etch back process with respect to the first and second layers is approximately 1:1.

Abstract translation: 提供了一种使半导体器件平坦化的方法。 该方法包括提供基板。 该方法包括在衬底上形成第一层。 该方法包括在第一层上形成第二层。 第一层和第二层具有不同的材料组成。 该方法包括在第二层上形成第三层。 该方法包括在第三层上进行抛光处理，直到第三层基本上被去除。 该方法包括执行回蚀处理以去除第二层和第一层的一部分。 其中相对于第一层和第二层的蚀刻返回工艺的蚀刻选择性为约1:1。

公开(公告)号：US20120064720A1

公开(公告)日：2012-03-15

申请号：US12879664

申请日：2010-09-10

Applicant: Neng-Kuo Chen ,  Jeff J. Xu

Inventor： Neng-Kuo Chen ,  Jeff J. Xu

IPC: H01L21/306 ,  B05C11/00 ,  C23F1/08

CPC classification number: H01L21/32115 ,  H01L21/31051

Abstract: Provided is a method of planarizing a semiconductor device. The method includes providing a substrate. The method includes forming a first material layer on the substrate. The method includes forming a second material layer over the first material layer. The second material layer is softer than the first material layer and has an exposed surface that is not in contact with the first material layer. The method includes flattening the second material layer without removing a portion of the second material layer. The flattening is carried out in a manner such that the exposed surface is substantially flat after the flattening. The method includes performing an etch back process to remove the second material layer and a portion of the first material layer. Wherein an etching selectivity of the etch back process with respect to the first and second material layers is approximately 1:1.

Abstract translation: 提供了一种使半导体器件平坦化的方法。 该方法包括提供基板。 该方法包括在基底上形成第一材料层。 该方法包括在第一材料层上形成第二材料层。 第二材料层比第一材料层更软，并且具有不与第一材料层接触的暴露表面。 该方法包括使第二材料层变平而不去除第二材料层的一部分。 平坦化的方式使得露出的表面在平坦化之后基本上是平的。 该方法包括执行回蚀处理以去除第二材料层和第一材料层的一部分。 其中蚀刻反应过程相对于第一和第二材料层的蚀刻选择性为约1:1。

公开(公告)号：US20110151359A1

公开(公告)日：2011-06-23

申请号：US12980764

申请日：2010-12-29

Applicant: Ming-Feng Shieh ,  Shinn-Sheng Yu ,  Anthony Yen ,  Shao-Ming Yu ,  Chang-Yun Chang ,  Jeff J. Xu ,  Clement Hsingjen Wann

Inventor： Ming-Feng Shieh ,  Shinn-Sheng Yu ,  Anthony Yen ,  Shao-Ming Yu ,  Chang-Yun Chang ,  Jeff J. Xu ,  Clement Hsingjen Wann

IPC: G03F1/00 ,  G03F7/20 ,  G06F17/50

CPC classification number: H01L27/0203 ,  G03F1/00 ,  G03F1/36 ,  H01L21/3086 ,  H01L21/823431 ,  H01L29/66795

Abstract: Provided is a photolithography apparatus including a photomask. The photomask includes a pattern having a plurality, of features, in an example, dummy line features. The pattern includes a first region being in the form of a localized on-grid array and a second region where at least one of the features has an increased width. The apparatus may include a second photomask which may define an active region. The feature with an increased width may be adjacent, and outside, the defined active region.

Abstract translation: 提供了一种包括光掩模的光刻设备。 光掩模包括具有多个特征的图案，在示例中为假线特征。 该图案包括呈局部网格阵列形式的第一区域和其中至少一个特征具有增加的宽度的第二区域。 该装置可以包括可以限定有源区域的第二光掩模。 具有增加的宽度的特征可以与所定义的有效区域相邻并且在外部。

公开(公告)号：US07910453B2

公开(公告)日：2011-03-22

申请号：US12172687

申请日：2008-07-14

Applicant: Jeff J. Xu ,  Chia-Ta Hsieh ,  Chun-Pei Wu ,  Chun-Hung Lee

Inventor： Jeff J. Xu ,  Chia-Ta Hsieh ,  Chun-Pei Wu ,  Chun-Hung Lee

IPC: H01L21/76

CPC classification number: H01L27/11568 ,  H01L29/4234 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure provides a method of manufacturing a microelectronic device. The method includes forming recessed shallow trench isolation (STI) features in a semiconductor substrate, defining a semiconductor region between adjacent two of the recessed STI features; forming a tunnel dielectric feature within the semiconductor region; forming a nitride layer on the recessed STI features and the tunnel dielectric feature; etching the nitride layer to form nitride openings within the recessed STI features; partially removing the recessed STI features through the nitride openings, resulting in gaps between the nitride layer and the recessed STI features; and forming a first dielectric material on surfaces of the nitride layer, sealing the nitride openings.

Abstract translation: 本公开提供了一种制造微电子器件的方法。 该方法包括在半导体衬底中形成凹陷的浅沟槽隔离（STI）特征，在相邻的两个凹入STI特征之间限定半导体区域; 在所述半导体区域内形成隧道电介质特征; 在凹陷的STI特征和隧道电介质特征上形成氮化物层; 蚀刻氮化物层以在凹陷STI特征内形成氮化物开口; 通过氮化物开口部分地去除凹陷的STI特征，导致氮化物层和凹陷STI特征之间的间隙; 以及在所述氮化物层的表面上形成第一电介质材料，以密封所述氮化物开口。

公开(公告)号：US20100006974A1

公开(公告)日：2010-01-14

申请号：US12172687

申请日：2008-07-14

Applicant: Jeff J. Xu ,  Chia-Ta Hsieh ,  Chun-Pei Wu ,  Chun-Hung Lee

Inventor： Jeff J. Xu ,  Chia-Ta Hsieh ,  Chun-Pei Wu ,  Chun-Hung Lee

IPC: H01L23/58 ,  H01L21/762

CPC classification number: H01L27/11568 ,  H01L29/4234 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure provides a method of manufacturing a microelectronic device. The method includes forming recessed shallow trench isolation (STI) features in a semiconductor substrate, defining a semiconductor region between adjacent two of the recessed STI features; forming a tunnel dielectric feature within the semiconductor region; forming a nitride layer on the recessed STI features and the tunnel dielectric feature; etching the nitride layer to form nitride openings within the recessed STI features; partially removing the recessed STI features through the nitride openings, resulting in gaps between the nitride layer and the recessed STI features; and forming a first dielectric material on surfaces of the nitride layer, sealing the nitride openings.

Abstract translation: 本公开提供了一种制造微电子器件的方法。 该方法包括在半导体衬底中形成凹陷的浅沟槽隔离（STI）特征，在相邻的两个凹入的STI特征之间限定半导体区域; 在所述半导体区域内形成隧道电介质特征; 在凹陷的STI特征和隧道电介质特征上形成氮化物层; 蚀刻氮化物层以在凹陷STI特征内形成氮化物开口; 通过氮化物开口部分地去除凹陷的STI特征，导致氮化物层和凹陷STI特征之间的间隙; 以及在所述氮化物层的表面上形成第一电介质材料，以密封所述氮化物开口。

公开(公告)号：US20090203217A1

公开(公告)日：2009-08-13

申请号：US12029834

申请日：2008-02-12

Applicant: Chun-Hung Lee ,  Chia-Chi Chung ,  Hsin-Chih Chen ,  Jeff J. Xu ,  Neng-Kuo Chen

Inventor： Chun-Hung Lee ,  Chia-Chi Chung ,  Hsin-Chih Chen ,  Jeff J. Xu ,  Neng-Kuo Chen

IPC: H01L21/302

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139

Abstract: A method is disclosed for etching an integrated circuit structure within a trench. A layer to be etched is applied over the structure and within the trench. A CF-based polymer is deposited over the layer to be etched followed by deposition of a capping layer of SiOCl-based polymer. The CF-based polymer reduces the width of the trench to such an extent that little or no SiOCl-based polymer is deposited at the bottom of the trench. An O2 plasma etch is performed to etch through the CF-based polymer at the bottom of the trench. The O2 plasma etch has little effect on the SiOCl-based polymer, the thus the upper surfaces of the structure remain covered with polymer. Thus, these upper surfaces remain fully protected during subsequent etching of the layer to be etched.

Abstract translation: 公开了一种用于蚀刻沟槽内的集成电路结构的方法。 待蚀刻的层被施加在结构之上和沟槽内。 将CF基聚合物沉积在待蚀刻的层上，随后沉积SiOCl基聚合物的覆盖层。 基于CF的聚合物将沟槽的宽度减小到在沟槽底部沉积少量或不存在SiOCl基聚合物的程度。 执行O2等离子体蚀刻以在沟槽的底部蚀刻通过CF基聚合物。 O2等离子体蚀刻对SiOCl基聚合物几乎没有影响，因此结构的上表面保持被聚合物覆盖。 因此，在随后蚀刻待蚀刻的层期间，这些上表面保持完全保护。

公开(公告)号：US08623728B2

公开(公告)日：2014-01-07

申请号：US12831842

申请日：2010-07-07

Applicant: Chih-Hao Chang ,  Jeff J. Xu ,  Chien-Hsun Wang ,  Chih Chieh Yeh ,  Chih-Hsiang Chang

Inventor： Chih-Hao Chang ,  Jeff J. Xu ,  Chien-Hsun Wang ,  Chih Chieh Yeh ,  Chih-Hsiang Chang

IPC: H01L21/336 ,  H01L21/31 ,  H01L21/469 ,  H01L21/00

CPC classification number: H01L29/785 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/18 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method for producing a SiGe stressor with high Ge concentration is provided. The method includes providing a semiconductor substrate with a source area, a drain area, and a channel in between; depositing the first SiGe film layer on the source area and/or the drain area; performing a low temperature thermal oxidation, e.g., a high water vapor pressure wet oxidation, to form an oxide layer at the top of the first SiGe layer and to form the second SiGe film layer with high Ge percentage at the bottom of the first SiGe film layer without Ge diffusion into the semiconductor substrate; performing a thermal diffusion to form the SiGe stressor from the second SiGe film layer, wherein the SiGe stressor provides uniaxial compressive strain on the channel; and removing the oxide layer. A Si cap layer can be deposited on the first SiGe film layer prior to performing oxidation.

Abstract translation: 提供了具有高Ge浓度的SiGe应激源的制造方法。 该方法包括：提供具有源极区域，漏极区域和沟道之间的半导体衬底; 在源极区域和/或漏极区域上沉积第一SiGe膜层; 进行低温热氧化，例如高水蒸气压湿氧化，以在第一SiGe层的顶部形成氧化物层，并在第一SiGe膜的底部形成具有高Ge百分比的第二SiGe膜层 Ge层扩散到半导体衬底中; 执行热扩散以从第二SiGe膜层形成SiGe应力源，其中SiGe应力源在通道上提供单轴压缩应变; 并除去氧化物层。 在进行氧化之前，可以在第一SiGe膜层上淀积Si覆盖层。

公开(公告)号：US08597995B2

公开(公告)日：2013-12-03

申请号：US13244358

申请日：2011-09-24

Applicant: Jeff J. Xu

Inventor： Jeff J. Xu

IPC: H01L21/8238

CPC classification number: H01L21/28088 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78

Abstract: A semiconductor device with a metal gate is disclosed. The device includes a semiconductor substrate, source and drain features on the semiconductor substrate, and a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes an interfacial layer (IL) layer, a high-k (HK) dielectric layer formed over the semiconductor substrate, an oxygen scavenging metal formed on top of the HK dielectric layer, a scaling equivalent oxide thickness (EOT) formed by using a low temperature oxygen scavenging technique, and a stack of metals gate layers deposited over the oxygen scavenging metal layer.

Abstract translation: 公开了一种具有金属栅极的半导体器件。 该器件包括半导体衬底，半导体衬底上的源极和漏极特征，以及位于半导体衬底上并设置在源极和漏极特征之间的栅极堆叠。 栅极堆叠包括界面层（IL）层，形成在半导体衬底上的高k（HK）电介质层，形成在HK电介质层顶部的氧清除金属，由 使用低温氧气清除技术，以及沉积在氧清除金属层上的金属栅层的堆叠。

公开(公告)号：US08501570B2

公开(公告)日：2013-08-06

申请号：US12981610

申请日：2010-12-30

Applicant: Ziwei Fang ,  Jeff J. Xu ,  Ming-Jie Huang ,  Yimin Huang ,  Zhiqiang Wu ,  Min Cao

Inventor： Ziwei Fang ,  Jeff J. Xu ,  Ming-Jie Huang ,  Yimin Huang ,  Zhiqiang Wu ,  Min Cao

IPC: H01L21/02 ,  H01L21/306 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L21/265

CPC classification number: H01L29/7848 ,  H01L21/02057 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/30604 ,  H01L21/30608 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78

Abstract: An integrated circuit device and method for manufacturing the integrated circuit device provide improved control over a shape of a trench for forming the source and drain features of integrated circuit device, by forming a second doped region in a first doped region and removing the first and the second doped regions by a first and a second wet etching processes.

Abstract translation: 用于制造集成电路器件的集成电路器件和方法通过在第一掺杂区域中形成第二掺杂区域并且去除第一和第二掺杂区域，从而提供对用于形成集成电路器件的源极和漏极特征的沟槽形状的改进的控制 第二掺杂区域通过第一和第二湿蚀刻工艺。

公开(公告)号：US20130056836A1

公开(公告)日：2013-03-07

申请号：US13224033

申请日：2011-09-01

Applicant: Xiong-Fei Yu ,  Chun-Yuan Chou ,  Da-Yuan Lee ,  Kuan-Yuan Hsu ,  Jeff J. Xu

Inventor： Xiong-Fei Yu ,  Chun-Yuan Chou ,  Da-Yuan Lee ,  Kuan-Yuan Hsu ,  Jeff J. Xu

IPC: H01L29/772 ,  H01L21/336

CPC classification number: H01L27/092 ,  H01L21/28088 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/32051 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7848

Abstract: A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.

Abstract translation: 公开了一种具有金属栅极的半导体器件。 具有金属栅极的示例性半导体器件包括半导体衬底，半导体衬底上的源极和漏极特征，半导体衬底上的栅极堆叠并且设置在源极和漏极特征之间。 所述栅堆叠包括形成在所述半导体衬底上的HK电介质层，形成在所述HK电介质层的顶部上的金属化合物的多个势垒层，其中每个所述阻挡层具有不同的化学组成; 以及沉积在所述多个阻挡层上的一叠金属栅极层。