公开(公告)号：US07598169B2

公开(公告)日：2009-10-06

申请号：US11677100

申请日：2007-02-21

申请人： Qinghuang Lin ,  Elbert E. Huang ,  Christy S. Tyberg ,  Ronald A. DellaGuardia

发明人： Qinghuang Lin ,  Elbert E. Huang ,  Christy S. Tyberg ,  Ronald A. DellaGuardia

IPC分类号： H01L21/4763

CPC分类号： H01L21/31127 ,  H01L21/02063 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76826

摘要： A method to fabricate interconnect structures that are part of integrated circuits and microelectronic devices by utilization of an irradiation to remove and clean a sacrificial material used therein is described. The advantages of utilizing the irradiation to remove the sacrificial material include reduced damage to interlayer dielectric layers that result in enhanced device performance and/or increased reliability.

摘要翻译： 描述了通过利用照射去除和清洁其中使用的牺牲材料来制造作为集成电路和微电子器件的一部分的互连结构的方法。 利用照射去除牺牲材料的优点包括降低对层间电介质层的损伤，导致增强的器件性能和/或增加的可靠性。

公开(公告)号：US20080173984A1

公开(公告)日：2008-07-24

申请号：US11626550

申请日：2007-01-24

申请人： Qinghuang Lin ,  Terry A. Spooner ,  Darshan D. Gandhi ,  Christy S. Tyberg

发明人： Qinghuang Lin ,  Terry A. Spooner ,  Darshan D. Gandhi ,  Christy S. Tyberg

IPC分类号： H01L23/58 ,  H01L21/31

CPC分类号： H01L21/3105 ,  H01L21/76805 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76834

摘要： A mechanically robust semiconductor structure with improved adhesion strength between a low-k dielectric layer and a dielectric-containing substrate is provided. In particular, the present invention provides a structure that includes a dielectric-containing substrate having an upper region including a treated surface layer which is chemically and physically different from the substrate; and a low-k dielectric material located on a the treated surface layer of the substrate. The treated surface layer and the low-k dielectric material form an interface that has an adhesion strength that is greater than 60% of the cohesive strength of the weaker material on either side of the interface. The treated surface is formed by treating the surface of the substrate with at least one of actinic radiation, a plasma and e-beam radiation prior to forming of the substrate the low-k dielectric material.

摘要翻译： 提供了具有改善的低k电介质层和含电介质衬底之间的粘附强度的机械稳固的半导体结构。 特别地，本发明提供了一种结构，其包括含电介质的衬底，其具有包括化学和物理上不同于衬底的经处理的表面层的上部区域; 以及位于所述基板的经处理的表面层上的低k电介质材料。 经处理的表面层和低k电介质材料形成界面，该界面的粘合强度大于界面两侧的较弱材料的内聚强度的60％。 经处理的表面通过在形成低k电介质材料之前用光化辐射，等离子体和电子束辐射中的至少一种来处理衬底的表面而形成。

公开(公告)号：US20110207286A1

公开(公告)日：2011-08-25

申请号：US13100456

申请日：2011-05-04

申请人： Geoffrey W. Burr ,  Chandrasekharan Kothandaraman ,  Chung Hon Lam ,  Xiao Hu Liu ,  Stephen M. Rossnagel ,  Christy S. Tyberg ,  Robert L. Wisnieff

发明人： Geoffrey W. Burr ,  Chandrasekharan Kothandaraman ,  Chung Hon Lam ,  Xiao Hu Liu ,  Stephen M. Rossnagel ,  Christy S. Tyberg ,  Robert L. Wisnieff

IPC分类号： H01L21/768

CPC分类号： H01L23/5256 ,  H01L23/5252 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/1226 ,  H01L45/1286 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1683 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A reversible fuse structure in an integrated circuit is obtained through the implementation of a fuse cell having a short thin line of phase change materials in contact with via and line structures capable of passing current through the line of phase change material (fuse cell). The current is passed through the fuse cell in order to change the material from a less resistive material to a more resistive material through heating the phase change material in the crystalline state to the melting point then quickly quenching the material into the amorphous state. The reversible programming is achieved by passing a lower current through the fuse cell to convert the high resistivity amorphous material to a lower resistivity crystalline material. Appropriate sense-circuitry is integrated to read the information stored in the fuses, wherein said sense circuitry is used to enable or disable circuitry.

摘要翻译： 集成电路中的可逆熔丝结构通过实现具有短路相变材料的熔断电池获得，所述相变材料与能够使电流通过相变材料线（熔丝电池）的通孔和线结构相接触。 电流通过熔丝电池，以便通过将结晶状态的相变材料加热至熔点，从而将材料从较小电阻的材料转变为更电阻的材料，然后快速将材料淬火成非晶状态。 可逆编程通过使较低电流通过熔丝电池来实现，以将高电阻率无定形材料转换成较低电阻率的晶体材料。 集成适当的感测电路以读取存储在熔丝中的信息，其中所述感测电路用于启用或禁用电路。

公开(公告)号：US20100006850A1

公开(公告)日：2010-01-14

申请号：US12561827

申请日：2009-09-17

申请人： Christy S. Tyberg ,  Katherine L. Saenger ,  Jack O. Chu ,  Harold J. Hovel ,  Robert L. Wisnieff ,  Kerry Bernstein ,  Stephen W. Bedell

发明人： Christy S. Tyberg ,  Katherine L. Saenger ,  Jack O. Chu ,  Harold J. Hovel ,  Robert L. Wisnieff ,  Kerry Bernstein ,  Stephen W. Bedell

IPC分类号： H01L23/522 ,  H01L29/786 ,  H01L29/04

CPC分类号： H01L23/5226 ,  H01L23/53271 ,  H01L27/124 ,  H01L27/1248 ,  H01L2924/0002 ,  H01L2924/00

摘要： This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration.

摘要翻译： 本发明提供了用于在线路后端（BEOL）互连结构中并入薄膜晶体管的结构和制造工艺。 所描述的结构和制造工艺与BEOL互连结构的处理要求相兼容。 结构和制造工艺利用已经并入到互连布线层中的现有处理步骤和材料，以便降低与在这些层级中引入薄膜晶体管相关联的附加成本。 与现有技术的3D集成方法相比，该结构能够实现多层次的垂直（3D）集成，具有改进的可制造性和可靠性。

公开(公告)号：US20090046493A1

公开(公告)日：2009-02-19

申请号：US11838663

申请日：2007-08-14

申请人： SOLOMON ASSEFA ,  Michael C. Gaidis ,  Eric A. Joseph ,  Stuart Stephen Papworth Parkin ,  Christy S. Tyberg

发明人： SOLOMON ASSEFA ,  Michael C. Gaidis ,  Eric A. Joseph ,  Stuart Stephen Papworth Parkin ,  Christy S. Tyberg

IPC分类号： G11C19/08 ,  H01L21/00

CPC分类号： H01L27/222 ,  B82Y10/00 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C19/0808 ,  H01L21/76816 ,  H01L43/08

摘要： In one embodiment, the invention is a method and apparatus for fabricating sub-lithography data tracks for use in magnetic shift register memory devices. One embodiment of a memory device includes a first stack of dielectric material formed of a first dielectric material, a second stack of dielectric material surrounding the first stack of dielectric material and formed of at least a second dielectric material, and at least one data track for storing information, positioned between the first stack of dielectric material and the second stack of dielectric material, the data track having a high aspect ratio and a substantially rectangular cross section.

摘要翻译： 在一个实施例中，本发明是用于制造用于磁移位寄存器存储器件的子光刻数据磁道的方法和装置。 存储器件的一个实施例包括由第一电介质材料形成的介电材料的第一叠层，围绕第一电介质材料堆叠并由至少第二电介质材料形成的第二电介质材料叠层，以及至少一个用于 存储位于所述第一电介质材料堆叠和所述第二电介质材料堆之间的信息，所述数据轨道具有高纵横比和基本上矩形的横截面。

公开(公告)号：US20080224118A1

公开(公告)日：2008-09-18

申请号：US12127994

申请日：2008-05-28

申请人： James P. Doyle ,  Bruce G. Elmegreen ,  Lia Krusin-Elbaum ,  Chung Hon Lam ,  Xiao Hu Liu ,  Dennis M. Newns ,  Christy S. Tyberg

发明人： James P. Doyle ,  Bruce G. Elmegreen ,  Lia Krusin-Elbaum ,  Chung Hon Lam ,  Xiao Hu Liu ,  Dennis M. Newns ,  Christy S. Tyberg

IPC分类号： H01L47/00

CPC分类号： H01L45/1233 ,  G11C13/0004 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/1286 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1666

摘要： An electrically re-programmable fuse (eFUSE) device for use in integrated circuit devices includes an elongated heater element, an electrically insulating liner surrounding an outer surface of the elongated heater element, corresponding to a longitudinal axis thereof, leaving opposing ends of the elongated heater element in electrical contact with first and second heater electrodes. A phase change material (PCM) surrounds a portion of an outer surface of the electrically insulating liner, a thermally and electrically insulating layer surrounds an outer surface of the PCM, with first and second fuse electrodes in electrical contact with opposing ends of the PCM. The PCM is encapsulated within the electrically insulating liner, the thermally and electrically insulating layer, and the first and second fuse electrodes.

公开(公告)号：US20080128766A1

公开(公告)日：2008-06-05

申请号：US12030921

申请日：2008-02-14

申请人： Elbert E. Huang ,  Philip J. Oldiges ,  Ghavam G. Shahidi ,  Christy S. Tyberg ,  Xinlin Wang ,  Robert L. Wisnieff

发明人： Elbert E. Huang ,  Philip J. Oldiges ,  Ghavam G. Shahidi ,  Christy S. Tyberg ,  Xinlin Wang ,  Robert L. Wisnieff

IPC分类号： H01L29/94 ,  H01L21/336

CPC分类号： H01L29/4991 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A MOSFET structure and method of fabricating the structure incorporates a multi-layer sidewall spacer to suppress parasitic overlap capacitance between the gate conductor and the source/drain extensions without degrading drive current and, thereby, effecting overall MOSFET performance. The multi-layer sidewall spacer is formed with a gap layer having a dielectric constant equal to one and a permeable low-K (e.g., less than 3.5) dielectric layer. Alternatively, the multi-layer sidewall spacer is formed with a first L-shaped dielectric layer having a permittivity value of less than approximately three and a second dielectric layer. The multi-layer spacer may also have a third nitride or oxide spacer layer. This third spacer layer provides increased structural integrity.

摘要翻译： MOSFET结构和制造该结构的方法包括多层侧壁间隔物，以抑制栅极导体和源极/漏极延伸之间的寄生重叠电容，而不降低驱动电流，从而影响整体MOSFET性能。 多层侧壁间隔物形成有介电常数等于1的间隙层和可渗透的低K（例如，小于3.5）的电介质层。 或者，多层侧壁间隔物形成有介电常数值小于约三的第一L形介电层和第二电介质层。 多层间隔物也可以具有第三氮化物或氧化物隔离层。 该第三间隔层提供增加的结构完整性。

公开(公告)号：US06674168B1

公开(公告)日：2004-01-06

申请号：US10248452

申请日：2003-01-21

申请人： Edward C. Cooney, III ,  Robert M Geffken ,  Vincent J McGahay ,  William T. Motsiff ,  Mark P. Murray ,  Amanda L. Piper ,  Anthony K. Stamper ,  David C. Thomas ,  Christy S. Tyberg ,  Elizabeth T. Webster

发明人： Edward C. Cooney, III ,  Robert M Geffken ,  Vincent J McGahay ,  William T. Motsiff ,  Mark P. Murray ,  Amanda L. Piper ,  Anthony K. Stamper ,  David C. Thomas ,  Christy S. Tyberg ,  Elizabeth T. Webster

IPC分类号： H01L2100

CPC分类号： H01L21/76808 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76892 ,  H01L23/525 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of reworking BEOL (back end of a processing line) metallization levels of damascene metallurgy comprises forming a plurality of BEOL metallization levels over a substrate, forming line and via portions in the BEOL metallization levels, selectively removing at least one of the BEOL metallization levels to expose the line and via portions, and replacing the removed BEOL metallization levels with at least one new BEOL metallization level, wherein the BEOL metallization levels comprise a first dielectric layer and a second dielectric layer, and wherein the first dielectric layer comprising a lower dielectric constant material than the second dielectric layer.

摘要翻译： 一种重新加工BEOL（处理线的后端）金刚石冶金的金​​属化水平的方法包括在衬底上形成多个BEOL金属化水平，在BEOL金属化水平中形成线和通孔部分，选择性地去除BEOL金属化中的至少一个 以暴露线路和通孔部分，并且用至少一个新的BEOL金属化水平替换去除的BEOL金属化水平，其中BEOL金属化水平包括第一介电层和第二介电层，并且其中第一介电层包括下部 介电常数材料比第二介电层。

公开(公告)号：US08441042B2

公开(公告)日：2013-05-14

申请号：US12561827

申请日：2009-09-17

申请人： Christy S. Tyberg ,  Katherine L. Saenger ,  Jack O. Chu ,  Harold J. Hovel ,  Robert L. Wisnieff ,  Kerry Bernstein ,  Stephen W. Bedell

发明人： Christy S. Tyberg ,  Katherine L. Saenger ,  Jack O. Chu ,  Harold J. Hovel ,  Robert L. Wisnieff ,  Kerry Bernstein ,  Stephen W. Bedell

IPC分类号： H01L21/76

CPC分类号： H01L23/5226 ,  H01L23/53271 ,  H01L27/124 ,  H01L27/1248 ,  H01L2924/0002 ,  H01L2924/00

摘要： This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration.

摘要翻译： 本发明提供了用于在线路后端（BEOL）互连结构中并入薄膜晶体管的结构和制造工艺。 所描述的结构和制造工艺与BEOL互连结构的处理要求相兼容。 结构和制造工艺利用已经并入到互连布线层中的现有处理步骤和材料，以便降低与在这些层级中引入薄膜晶体管相关联的附加成本。 与现有技术的3D集成方法相比，该结构能够实现多层次的垂直（3D）集成，具有改进的可制造性和可靠性。

公开(公告)号：US20120305929A1

公开(公告)日：2012-12-06

申请号：US13572742

申请日：2012-08-13

申请人： Christy S. Tyberg ,  Katherine L. Saenger ,  Jack O. Chu ,  Harold J. Hovel ,  Robert L. Wisnieff ,  Kerry Bernstein ,  Stephen W. Bedell

发明人： Christy S. Tyberg ,  Katherine L. Saenger ,  Jack O. Chu ,  Harold J. Hovel ,  Robert L. Wisnieff ,  Kerry Bernstein ,  Stephen W. Bedell

IPC分类号： H01L29/786

CPC分类号： H01L23/5226 ,  H01L23/53271 ,  H01L27/124 ,  H01L27/1248 ,  H01L2924/0002 ,  H01L2924/00

摘要： This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration.

摘要翻译： 本发明提供了用于在线路后端（BEOL）互连结构中并入薄膜晶体管的结构和制造工艺。 所描述的结构和制造工艺与BEOL互连结构的处理要求相兼容。 结构和制造工艺利用已经并入到互连布线层中的现有处理步骤和材料，以便降低与在这些层级中引入薄膜晶体管相关联的附加成本。 与现有技术的3D集成方法相比，该结构能够实现多层次的垂直（3D）集成，具有改进的可制造性和可靠性。