公开(公告)号：US6165880A

公开(公告)日：2000-12-26

申请号：US94869

申请日：1998-06-15

申请人： Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Li-Chih Chao ,  Kuo Ching Huang

发明人： Dun-Nian Yaung ,  Shou-Gwo Wuu ,  Li-Chih Chao ,  Kuo Ching Huang

IPC分类号： H01L21/285 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/4763

CPC分类号： H01L21/76897 ,  H01L21/28525 ,  H01L21/32053

摘要： A method was achieved for making improved self-aligned contacts (SAC) to a patterned polysilicon layer, such as gate electrodes for FETs. Lightly doped source/drain areas are implanted. A second insulating layer is deposited and etched back to form first sidewall spacers. A silicon nitride etch-stop layer and a first interpolysilicon oxide (IPO1) layer are deposited. First SAC openings are etched in the IPO1 layer to the etch-stop layer, and concurrently openings are etched for the gate electrodes, eliminating a masking step. The etch-stop layer is etched in the SAC openings to form second sidewall spacers that protect the first sidewall spacers during BOE cleaning of the contacts. A patterned polycide layer is used to make SACs and electrical interconnections. A second IPO layer is deposited to provide insulation, and an interlevel dielectric layer is deposited. Second SAC openings are etched to the etch-stop layer for the next level of metal interconnections, while the contact openings to the gate electrodes are etched to completion. The etch-stop layer is etched in the second SAC openings to form second sidewall spacers to protect the first sidewall spacers during cleaning. Metal plugs are formed from a first metal in the second SAC openings and in the openings to the gate electrodes. A second metal is patterned to complete the structure to the first level of metal interconnections.

摘要翻译： 实现了对图案化多晶硅层（例如FET的栅电极）进行改进的自对准接触（SAC）的方法。 植入轻掺杂的源极/漏极区域。 沉积第二绝缘层并回蚀刻以形成第一侧壁间隔物。 沉积氮化硅蚀刻停止层和第一多晶硅化硅（IPO1）层。 在IPO1层中蚀刻第一SAC开口到蚀刻停止层，同时蚀刻用于栅电极的开口，从而消除掩模步骤。 在SAC开口中蚀刻蚀刻停止层以形成第二侧壁间隔物，其在接触的BOE清洁期间保护第一侧壁间隔物。 使用图案化的多晶硅化合物层来制造SAC和电互连。 沉积第二个IPO层以提供绝缘，并且沉积层间电介质层。 将第二SAC开口蚀刻到蚀刻停止层以进行下一级金属互连，同时蚀刻到栅电极的接触开口以完成。 在第二SAC开口中蚀刻蚀刻停止层以形成第二侧壁间隔物，以在清洁期间保护第一侧壁间隔物。 金属插塞由第二SAC开口中的第一金属和与栅电极的开口形成。 图案化第二金属以将结构完成到第一级金属互连。

公开(公告)号：US6140218A

公开(公告)日：2000-10-31

申请号：US329782

申请日：1999-06-10

申请人： Jen-Cheng Liu ,  Li-Chih Chao ,  Huan-Just Lin ,  Yung-Kuan Hsiao

发明人： Jen-Cheng Liu ,  Li-Chih Chao ,  Huan-Just Lin ,  Yung-Kuan Hsiao

IPC分类号： H01L21/033 ,  H01L21/28 ,  H01L21/60 ,  H01L21/44

CPC分类号： H01L21/76897 ,  H01L21/0334 ,  H01L21/28123

摘要： The present invention provides a method of fabricating a T-shaped hard mask/conductive pattern profile and a process of etching a self-aligned contact opening using a T-shaped hard mask/conductive pattern profile to improve the self-aligned contact isolation. The process begins by forming a polysilicon or more preferably a polysilicon/silicide conductive layer over a semiconductor substrate. A silicon oxynitride hard mask layer is formed over the conductive layer. The silicon oxynitride hard mask layer is patterned to form a hard mask pattern. The conductive layer is patterned to form a conductive pattern in a three step etch using Cl.sub.2 and HBr chemistry. The silicon oxynitride hard mask releases oxygen during the conductive layer etch resulting in a T-shaped hard mask/conductive pattern profile (e.g. the width of the hard mask is greater than the width of the conductive pattern after etching). In a preferred embodiment, the a T-shaped hard mask/conductive pattern profile is used to form a self-aligned contact for a capacitor over bitline structure.

摘要翻译： 本发明提供了一种制造T形硬掩模/导电图案轮廓的方法以及使用T形硬掩模/导电图案轮廓蚀刻自对准接触开口的过程，以改善自对准接触隔离。 该过程通过在半导体衬底上形成多晶硅或更优选多晶硅/硅化物导电层开始。 在导电层上形成氧氮化硅硬掩模层。 将氮氧化硅硬掩模层图案化以形成硬掩模图案。 使用Cl2和HBr化学，在三步蚀刻中对导电层进行图案化以形成导电图案。 氧氮化硅硬掩模在导电层蚀刻期间释放氧，导致T形硬掩模/导电图案轮廓（例如，硬掩模的宽度大于蚀刻后的导电图案的宽度）。 在优选实施例中，T形硬掩模/导电图形轮廓用于通过位线结构形成用于电容器的自对准接触。

公开(公告)号：US20050014362A1

公开(公告)日：2005-01-20

申请号：US10915633

申请日：2004-08-10

申请人： Bang-Chien Ho ,  Jian-Hong Chen ,  Tsang-Jiuh Wu ,  Li-Te Lin ,  Li-Chih Chao ,  Hua-Tai Lin ,  Shyue-Sheng Lu

发明人： Bang-Chien Ho ,  Jian-Hong Chen ,  Tsang-Jiuh Wu ,  Li-Te Lin ,  Li-Chih Chao ,  Hua-Tai Lin ,  Shyue-Sheng Lu

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76808

摘要： A method of fabricating semiconductor devices using dual damascene processes to form plugs in the via holes composed of various high etch materials and bottom anti-reflection coating (BARC) materials. After via hole etch, a layer of high etch rate plug material is spin coated to fill the via holes. Next, a layer of photoresist is applied. The photoresist is then exposed through a mask and developed to form an etch opening. Using the remaining photoresist as an etch mask and with a bottom anti-reflection coating (BARC) as protection, the oxide or low k layer is etched to form subsequent wiring. The etch step is known as a damascene etch step. The remaining photoresist is removed and the trench/via openings are filled with metal forming inlaid metal interconnect wiring and contact vias.

摘要翻译： 使用双镶嵌工艺制造半导体器件的方法来在由各种高蚀刻材料和底部抗反射涂层（BARC）材料构成的通孔中形成插塞。 在通孔蚀刻之后，旋涂一层高蚀刻速率的塞材料以填充通孔。 接下来，施加一层光致抗蚀剂。 然后将光致抗蚀剂通过掩模曝光并显影以形成蚀刻开口。 使用剩余的光致抗蚀剂作为蚀刻掩模和底部防反射涂层（BARC）作为保护，氧化物或低k层被蚀刻以形成后续布线。 蚀刻步骤被称为镶嵌蚀刻步骤。 去除剩余的光致抗蚀剂，并且通过金属形成金属互连布线和接触通孔填充沟槽/通孔开口。

公开(公告)号：US06457477B1

公开(公告)日：2002-10-01

申请号：US09624020

申请日：2000-07-24

申请人： Bao-Ru Young ,  Li-Chih Chao ,  Shwangming Jeng ,  Chi-Shiung Tsai

发明人： Bao-Ru Young ,  Li-Chih Chao ,  Shwangming Jeng ,  Chi-Shiung Tsai

IPC分类号： H01L21302

CPC分类号： H01L21/76814 ,  H01L21/76807 ,  Y10S134/902 ,  Y10S438/906 ,  Y10S438/963

摘要： A method of cleaning a low-k material etched opening, comprising the following steps. A semiconductor structure having an exposed device therein is provided. An etch stop layer is formed over the semiconductor structure and the exposed device. A layer of low-k material is formed over the etch stop layer semiconductor structure and device. A patterned layer of photoresist is formed over the low-k material layer. The patterned photoresist layer is used as a mask to etch low-k material layer is etched to form an opening exposing at least a portion of the etch stop layer over the device. The patterned photoresist layer is removed by a low temperature ashing process at a temperature from about 23 to 27° C., and more preferably about 25° C. (room temperature). The exposed portion of the etch stop layer over the device is removed to expose the underlying device by a low pressure, low bias etching process at a pressure from about 8 to 12 milli-Torr and a bias power from about 25 to 35 W. The exposed underlying device and the opening are cleaned by removing any remaining low pressure, low bias etch polymer and etch residue by a fully dry-type cleaning process using an H2He gas.

摘要翻译： 一种清洁低k材料蚀刻开口的方法，包括以下步骤。 提供其中具有暴露设备的半导体结构。 在半导体结构和暴露的器件上形成蚀刻停止层。 在蚀刻停止层半导体结构和器件上形成一层低k材料。 在低k材料层上形成图案化的光致抗蚀剂层。 图案化的光致抗蚀剂层用作掩模以蚀刻低k材料层被蚀刻以形成暴露在该器件上的蚀刻停止层的至少一部分的开口。 通过低温灰化过程在约23至27℃，更优选约25℃（室温）的温度下除去图案化的光致抗蚀剂层。 去除器件上的蚀刻停止层的暴露部分，通过低压，低偏压蚀刻工艺在约8至12毫乇的压力和约25至35瓦的偏压功率下暴露下层器件。 通过使用H2He气体通过完全干式清洁方法除去任何剩余的低压，低偏压蚀刻聚合物和蚀刻残留物来清洁露出的下部器件和开口。

公开(公告)号：US06184149B2

公开(公告)日：2001-02-06

申请号：US08918315

申请日：1997-08-26

申请人： Li-Chih Chao ,  Yuan-Chang Huang

发明人： Li-Chih Chao ,  Yuan-Chang Huang

IPC分类号： H01L21302

CPC分类号： H01L21/76897 ,  H01L21/31116 ,  H01L22/20

摘要： The present invention provides a method for monitoring a self-aligned contact (SAC) etching process. A wafer with an oxide layer serves as an oxide control wafer. The oxide layer is formed on the substrate. The oxide control wafer and a SAC wafer with SAC structure are simultaneously treated with a SAC etching process in an etching chamber with the same etching recipe. A contact hole is formed by etching the oxide layer of the oxide control wafer after the SAC etching process. The depth of a profile transition point and the depth of etching stop for the oxide control wafer can be observed by cross-section SEM. The profile transition depth in the oxide control wafer corresponds to the etching thickness of SiN corner loss in the SAC wafer. Therefore, the profile transition depth and the depth of etching stop in the oxide control wafer can be used to monitor the etching chamber condition.

摘要翻译： 本发明提供一种用于监测自对准接触（SAC）蚀刻工艺的方法。 具有氧化物层的晶片用作氧化物控制晶片。 在基板上形成氧化物层。 具有SAC结构的氧化物控制晶片和SAC晶片在蚀刻室中用SAC蚀刻工艺同时用相同的蚀刻配方进行处理。 在SAC蚀刻工艺之后通过蚀刻氧化物控制晶片的氧化物层形成接触孔。 通过横截面SEM可以观察到轮廓转变点的深度和氧化物控制晶片的蚀刻停止深度。 氧化物控制晶片中的轮廓转移深度对应于SAC晶片中SiN角损失的蚀刻厚度。 因此，可以使用氧化物控制晶片中的轮廓转移深度和蚀刻停止深度来监测蚀刻室状况。

公开(公告)号：US6107206A

公开(公告)日：2000-08-22

申请号：US152350

申请日：1998-09-14

申请人： Li-Chih Chao ,  Chao-Cheng Chen

发明人： Li-Chih Chao ,  Chao-Cheng Chen

IPC分类号： H01L21/3065 ,  H01L21/762 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L21/3065 ,  H01L21/76232

摘要： A method of etching closely spaced trenches in a silicon body wherein a masked silicon body is introduced into a plasma etching apparatus. An object having an exposed silicon surface that is consumable by a plasma environment is provided in the apparatus. A reactive plasma environment is established in the apparatus which removes silicon from the body and the silicon object. The additional silicon from the object in the plasma influences the silicon removal from the body to thereby provide tapered trench side walls.

摘要翻译： 在硅体中蚀刻紧密间隔的沟槽的方法，其中将掩模的硅体引入等离子体蚀刻装置中。 在该装置中设置有具有由等离子体环境消耗的暴露的硅表面的物体。 在从身体和硅物体中去除硅的装置中建立了反应等离子体环境。 来自等离子体中的物体的附加硅影响硅体从硅体移除，从而提供锥形的沟槽侧壁。

公开(公告)号：US07253112B2

公开(公告)日：2007-08-07

申请号：US10915633

申请日：2004-08-10

申请人： Bang-Chien Ho ,  Jian-Hong Chen ,  Tsang-Jiuh Wu ,  Li-Te Lin ,  Li-Chih Chao ,  Hua-Tai Lin ,  Shyue-Sheng Lu

发明人： Bang-Chien Ho ,  Jian-Hong Chen ,  Tsang-Jiuh Wu ,  Li-Te Lin ,  Li-Chih Chao ,  Hua-Tai Lin ,  Shyue-Sheng Lu

IPC分类号： H01L21/311

CPC分类号： H01L21/76808

摘要： A method of fabricating semiconductor devices using dual damascene processes to form plugs in the via holes composed of various high etch materials and bottom anti-reflection coating (BARC) materials. After via hole etch, a layer of high etch rate plug material is spin coated to fill the via holes. Next, a layer of photoresist is applied. The photoresist is then exposed through a mask and developed to form an etch opening. Using the remaining photoresist as an etch mask and with a bottom anti-reflection coating (BARC) as protection, the oxide or low k layer is etched to form subsequent wiring. The etch step is known as a damascene etch step. The remaining photoresist is removed and the trench/via openings are filled with metal forming inlaid metal interconnect wiring and contact vias.

摘要翻译： 使用双镶嵌工艺制造半导体器件的方法来在由各种高蚀刻材料和底部抗反射涂层（BARC）材料组成的通孔中形成插塞。 在通孔蚀刻之后，旋涂一层高蚀刻速率的塞材料以填充通孔。 接下来，施加一层光致抗蚀剂。 然后将光致抗蚀剂通过掩模曝光并显影以形成蚀刻开口。 使用剩余的光致抗蚀剂作为蚀刻掩模和底部防反射涂层（BARC）作为保护，氧化物或低k层被蚀刻以形成后续布线。 蚀刻步骤被称为镶嵌蚀刻步骤。 去除剩余的光致抗蚀剂，并且通过金属形成金属互连布线和接触通孔填充沟槽/通孔开口。

公开(公告)号：US06429119B1

公开(公告)日：2002-08-06

申请号：US09405059

申请日：1999-09-27

申请人： Li-Chih Chao ,  Chia-Shiung Tsai ,  Ming-Huei Lui ,  Jen-Cheng Liu ,  Chao-Cheng Chen

发明人： Li-Chih Chao ,  Chia-Shiung Tsai ,  Ming-Huei Lui ,  Jen-Cheng Liu ,  Chao-Cheng Chen

IPC分类号： H01L214763

CPC分类号： H01L21/76808 ,  H01L21/76813 ,  H01L2221/1063

摘要： Using this special dual damascene process, interconnect conducting lines and via contacts are formed which have low parasitic capacitance (low RC time constants). The invention incorporates the use of thin etch stop or etch barrier layers. The key process steps of this invention are a special partial via hole etch and a special via hole liner. The Prior Art dual damascene processes are generally composed of a thick via etch stop layer to avoid damaging underlying Cu during via patterning, as well as, a thick trench etch stop layer to avoid via hole facet during trench patterning. Thick etch stop layers are undesirably due to high dielectric constant values compared with silicon oxide, the intermetal dielectric (IMD). Therefore, the thickness of stop-layer should be reduced to minimize the circuit (RC) time constant delay. In general, there are two main approaches for dual damascene etching. One of the main approaches use self-aligned dual damascene (SADD) etching which requires a thick trench etching stop-layer thickness. The other approach use counter-bore method which requires a thick via etching stop-layer thickness. This invention describes a novel dual damascene process which can minimize the thickness of both via and trench etching stop-layer, while avoiding deleterious damage to the underlying to and via facet profile during via and trench etching.

摘要翻译： 使用这种特殊的双镶嵌工艺，形成具有低寄生电容（低RC时间常数）的互连导线和通孔触点。 本发明包括使用薄蚀刻停止层或蚀刻阻挡层。 本发明的关键工艺步骤是特殊的部分通孔蚀刻和特殊通孔衬垫。 现有技术的双镶嵌工艺通常由厚的通孔蚀刻停止层组成，以避免在通孔图案化期间损坏下面的铜，以及在沟槽图案化期间避免通孔小面的厚沟槽蚀刻停止层。 与氧化硅（金属间电介质（IMD））相比，由于高的介电常数值，厚的蚀刻停止层是不期望的。 因此，应该减小停止层的厚度以最小化电路（RC）时间常数延迟。 一般来说，双镶嵌蚀刻有两种主要方法。 主要方法之一使用自对准双镶嵌（SADD）蚀刻，其需要厚沟槽蚀刻停止层厚度。 另一种方法使用需要厚通孔蚀刻停止层厚度的反孔法。 本发明描述了一种新颖的双镶嵌工艺，其可以最小化通孔和沟槽蚀刻停止层的厚度，同时避免在通孔和沟槽蚀刻期间对于底面和经过小面轮廓的有害损伤。