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11.发明申请TRENCH-GATE FIELD EFFECT TRANSISTOR WITH CHANNEL ENHANCEMENT REGION AND METHODS OF FORMING THE SAME 有权具有通道增强区域的TRENCH-GATE场效应晶体管及其形成方法公开(公告)号：US20100258862A1
公开(公告)日：2010-10-14
申请号：US12698746
申请日：2010-02-02
申请人： Hamza Yilmaz , Daniel Calafut , Christopher Boguslaw Kocon , Steven P. Sapp , Dean E. Probst , Nathan L. Kraft , Thomas E. Grebs , Rodney S. Ridley , Gary M. Dolny , Bruce D. Marchant , Joseph A. Yedinak
发明人： Hamza Yilmaz , Daniel Calafut , Christopher Boguslaw Kocon , Steven P. Sapp , Dean E. Probst , Nathan L. Kraft , Thomas E. Grebs , Rodney S. Ridley , Gary M. Dolny , Bruce D. Marchant , Joseph A. Yedinak
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7827 , H01L21/26586 , H01L29/0878 , H01L29/402 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/66666 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/872
摘要： A field effect transistor includes a body region of a first conductivity type in a semiconductor region of a second conductivity type. A gate trench extends through the body region and terminating within the semiconductor region. A source region of the second conductivity type extends in the body region adjacent the gate trench. The source region and an interface between the body region and the semiconductor region define a channel region therebetween which extends along the gate trench sidewall. A channel enhancement region of the second conductivity type is formed adjacent the gate trench. The channel enhancement region partially extends into a lower portion of the channel region to thereby reduce a resistance of the channel region.
摘要翻译： 场效应晶体管包括在第二导电类型的半导体区域中的第一导电类型的体区。 栅极沟槽延伸穿过身体区域并终止在半导体区域内。 第二导电类型的源极区域在与栅极沟槽相邻的体区中延伸。 源极区域和主体区域和半导体区域之间的界面限定其间沿着栅极沟槽侧壁延伸的沟道区域。 第二导电类型的沟道增强区域形成在栅极沟槽附近。 沟道增强区域部分地延伸到沟道区的下部，从而减小沟道区的电阻。
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公开(公告)号：US07595542B2
公开(公告)日：2009-09-29
申请号：US11375683
申请日：2006-03-13
IPC分类号： H01L29/93
CPC分类号： H01L29/0634 , H01L29/0696 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： A charge balance semiconductor power device comprises an active area having strips of p pillars and strips of n pillars arranged in an alternating manner, the strips of p and n pillars extending along a length of the active area. A non-active perimeter region surrounds the active area, and includes at least one p ring surrounding the active area. One end of at last one of the strips of p pillars extending immediately adjacent an edge of the active area terminates at a substantially straight line at which one end of each of the remainder of the strips of p pillars also end. The straight line extends perpendicular to the length of the active area along which the strips of n and p pillars extend.
摘要翻译： 电荷平衡半导体功率器件包括有源区，其具有p柱的条带和以交替方式布置的n个柱的条带，沿着有源区的长度延伸的p和n柱的条带。 非活动周边区域包围有源区域，并且包括围绕有源区域的至少一个p环。 最后一根直立在有源区域边缘上的p柱条的一端终止于大致直线，其中p柱的每条剩余的条的一端也结束。 直线垂直于有源区域的长度延伸，n和p柱的条带沿着该区域的长度延伸。
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13.发明授权Trench structure having one or more diodes embedded therein adjacent a PN junction 有权沟槽结构，其中一个或多个二极管嵌入其中，邻近PN结公开(公告)号：US07132712B2
公开(公告)日：2006-11-07
申请号：US10288982
申请日：2002-11-05
IPC分类号： H01L29/72
CPC分类号： H01L29/7816 , H01L29/0653 , H01L29/404 , H01L29/407 , H01L29/7802 , H01L29/7813 , H01L29/7818 , H01L29/861
摘要： In accordance with an embodiment of the invention, a semiconductor structure includes a semiconductor region having a P-type region and a N-type region forming a PN junction therebetween. A first trench extends in the semiconductor region adjacent at least one of the P-type and N-type regions. The first trench includes at least one diode therein.
摘要翻译： 根据本发明的实施例，半导体结构包括具有P型区域和在其间形成PN结的N型区域的半导体区域。 第一沟槽在邻近P型和N型区域中的至少一个的半导体区域中延伸。 第一沟槽在其中包括至少一个二极管。
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公开(公告)号：US07061066B2
公开(公告)日：2006-06-13
申请号：US10821796
申请日：2004-04-09
IPC分类号： H01L29/72
CPC分类号： H01L29/407 , H01L29/0653 , H01L29/0692 , H01L29/404 , H01L29/66143 , H01L29/861 , H01L29/872
摘要： In accordance with an embodiment of the invention, a Schottky diode includes a metal layer in contact with a semiconductor region to form a Schottky barrier therebetween. A first trench extends in the semiconductor region. The first trench includes at least one electrode or diode therein.
摘要翻译： 根据本发明的实施例，肖特基二极管包括与半导体区域接触以在其间形成肖特基势垒的金属层。 第一沟槽在半导体区域中延伸。 第一沟槽在其中包括至少一个电极或二极管。
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公开(公告)号：US20110241172A1
公开(公告)日：2011-10-06
申请号：US13083337
申请日：2011-04-08
CPC分类号： H01L29/7811 , H01L29/0615 , H01L29/0619 , H01L29/0634 , H01L29/402 , H01L29/41741
摘要： A silicon wafer includes a silicon region of first conductivity type and a plurality of strips of second conductivity type pillars extending in parallel in the silicon region from a location along a perimeter of the silicon wafer to an opposing location along the perimeter of the silicon wafer. The plurality of strips of second conductivity type pillars extend to a predetermined depth within the silicon region.
摘要翻译： 硅晶片包括第一导电类型的硅区域和多个第二导电类型的条带，其在硅区域中从沿着硅晶片的周边的位置平行延伸到沿着硅晶片的周边的相对位置。 第二导电型支柱的多条条延伸到硅区内的预定深度。
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16.发明授权Trench-gate field effect transistor with channel enhancement region and methods of forming the same 有权沟道栅场效应晶体管具有沟道增强区及其形成方法公开(公告)号：US07923776B2
公开(公告)日：2011-04-12
申请号：US12698746
申请日：2010-02-02
申请人： Hamza Yilmaz , Daniel Calafut , Christopher Boguslaw Kocon , Steven P. Sapp , Dean E. Probst , Nathan L. Kraft , Thomas E. Grebs , Rodney S. Ridley , Gary M. Dolny , Bruce D. Marchant , Joseph A. Yedinak
发明人： Hamza Yilmaz , Daniel Calafut , Christopher Boguslaw Kocon , Steven P. Sapp , Dean E. Probst , Nathan L. Kraft , Thomas E. Grebs , Rodney S. Ridley , Gary M. Dolny , Bruce D. Marchant , Joseph A. Yedinak
IPC分类号： H01L29/772
CPC分类号： H01L29/7827 , H01L21/26586 , H01L29/0878 , H01L29/402 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/66666 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/872
摘要： A field effect transistor includes a body region of a first conductivity type in a semiconductor region of a second conductivity type. A gate trench extends through the body region and terminating within the semiconductor region. A source region of the second conductivity type extends in the body region adjacent the gate trench. The source region and an interface between the body region and the semiconductor region define a channel region therebetween which extends along the gate trench sidewall. A channel enhancement region of the second conductivity type is formed adjacent the gate trench. The channel enhancement region partially extends into a lower portion of the channel region to thereby reduce a resistance of the channel region.
摘要翻译： 场效应晶体管包括在第二导电类型的半导体区域中的第一导电类型的体区。 栅极沟槽延伸穿过身体区域并终止在半导体区域内。 第二导电类型的源极区域在与栅极沟槽相邻的体区中延伸。 源极区域和主体区域和半导体区域之间的界面限定其间沿着栅极沟槽侧壁延伸的沟道区域。 第二导电类型的沟道增强区域形成在栅极沟槽附近。 沟道增强区域部分地延伸到沟道区的下部，从而减小沟道区的电阻。
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公开(公告)号：US07745846B2
公开(公告)日：2010-06-29
申请号：US12014581
申请日：2008-01-15
IPC分类号： H01L31/111 , H01L21/28
CPC分类号： H01L27/0727 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/40 , H01L29/41741 , H01L29/4175 , H01L29/41758 , H01L29/41766 , H01L29/4933 , H01L29/7806 , H01L29/782 , H01L29/872
摘要： A semiconductor device includes a substrate having a first conductivity type and a semiconductor layer formed over the substrate and having lower and upper surfaces. A laterally diffused metal-oxide-semiconductor (LDMOS) transistor device is formed over the substrate and includes a source region of the first conductivity type and a drain extension region of the first conductivity type formed in the semiconductor layer proximate the upper surface of the semiconductor layer, and a drain contact electrically connecting the drain extension region to the substrate. A Schottky diode is formed over the substrate and includes at least one doped region of the first conductivity type formed in the semiconductor layer proximate to the upper surface, an anode contact forming a Schottky barrier with the at least one doped region, and a cathode contact laterally spaced from the anode contact and electrically connecting at least one doped region to the substrate.
摘要翻译： 半导体器件包括具有第一导电类型的衬底和形成在衬底上并具有下表面和上表面的半导体层。 横向扩散的金属氧化物半导体（LDMOS）晶体管器件形成在衬底上，并且包括第一导电类型的源极区域和形成在靠近半导体的上表面的半导体层中的第一导电类型的漏极延伸区域 以及将漏极延伸区域与衬底电连接的漏极接触。 肖特基二极管形成在衬底之上，并且包括形成在靠近上表面的半导体层中的至少一个第一导电类型的掺杂区域，形成具有至少一个掺杂区域的肖特基势垒的阳极接触器和阴极接触器 与阳极接触件横向间隔开并将至少一个掺杂区域电连接到衬底。
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公开(公告)号：US07560787B2
公开(公告)日：2009-07-14
申请号：US11317653
申请日：2005-12-22
CPC分类号： H01L29/7811 , H01L29/407 , H01L29/41766 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： In accordance with an embodiment of the invention, a semiconductor power device includes an active region configured to conduct current when the semiconductor device is biased in a conducting state, and a termination region along a periphery of the active region. A first silicon region of a first conductivity type extends to a first depth within a second silicon region of a second conductivity type, the first and second silicon regions forming a PN junction therebetween. At least one termination trench is formed in the termination. The termination trench extends into the second silicon region, and is laterally spaced from the first silicon region. An insulating layer lines the sidewalls and bottom of the termination trench. A conductive electrode at least partially fills the termination trench.
摘要翻译： 根据本发明的实施例，半导体功率器件包括被配置为当半导体器件被偏置为导通状态时导通电流的有源区和沿着有源区的周边的端接区。 第一导电类型的第一硅区域延伸到第二导电类型的第二硅区域内的第一深度，第一和第二硅区域之间形成PN结。 在终端中形成至少一个终端沟槽。 端接沟槽延伸到第二硅区域中，并且与第一硅区域横向隔开。 绝缘层对终端沟槽的侧壁和底部进行排列。 导电电极至少部分地填充端接沟槽。
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19.发明授权Method for forming a shielded gate trench FET with the shield and gate electrodes being connected together 有权用于形成屏蔽栅沟槽FET的方法，其中屏蔽层和栅电极连接在一起公开(公告)号：US07473603B2
公开(公告)日：2009-01-06
申请号：US11938583
申请日：2007-11-12
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L21/823437 , H01L27/088 , H01L29/407 , H01L29/42368 , H01L29/66734 , H01L29/7811
摘要： A method of forming a field effect transistor includes the following steps. A trench is formed in a semiconductor region, and a shield dielectric layer lining lower sidewalls and a bottom surface of the trench is formed. A shield electrode is formed in a lower portion of the trench, and a dielectric layer is formed along upper trench sidewalls and over the shield electrode. A gate electrode is formed in the trench over the shield electrode, and an interconnect layer connecting the gate electrode and the shield electrode is formed.
摘要翻译： 形成场效应晶体管的方法包括以下步骤。 在半导体区域中形成沟槽，并形成衬套下侧壁和沟槽底面的屏蔽电介质层。 屏蔽电极形成在沟槽的下部，并且沿上沟槽侧壁和屏蔽电极上方形成电介质层。 在屏蔽电极上的沟槽中形成栅电极，形成连接栅电极和屏蔽电极的互连层。
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公开(公告)号：US07429523B2
公开(公告)日：2008-09-30
申请号：US11378087
申请日：2006-03-17
IPC分类号： H01L29/72
CPC分类号： H01L29/407 , H01L29/0653 , H01L29/0692 , H01L29/404 , H01L29/66143 , H01L29/861 , H01L29/872
摘要： a Schottky diode having a semiconductor region is formed as follows. A plurality of charge control electrodes are formed in the semiconductor region so as to influence an electric field in the semiconductor region, wherein at least two of the charge control electrodes are adapted to be biased differently from one another. The semiconductor region is overlaid with a metal layer to thereby form a Schottky barrier therebetween.
摘要翻译： 如下形成具有半导体区域的肖特基二极管。 多个电荷控制电极形成在半导体区域中，以便影响半导体区域中的电场，其中至少两个电荷控制电极适于彼此不同地偏置。 半导体区域被金属层覆盖，从而在它们之间形成肖特基势垒。
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