公开(公告)号：US20060189151A1

公开(公告)日：2006-08-24

申请号：US11384121

申请日：2006-03-17

申请人： Douglas Tweet ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Sheng Hsu

发明人： Douglas Tweet ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Sheng Hsu

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L31/035281 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/0265 ,  H01L31/101 ,  H01L31/1812 ,  Y02E10/50

摘要： Provided are a SiGe vertical optical path and a method for selectively forming a SiGe optical path normal structure for IR photodetection. The method comprises: forming a Si substrate surface; forming a Si feature, normal with respect to the Si substrate surface, such as a trench, via, or pillar; and, selectively forming a SiGe optical path overlying the Si normal feature. In some aspects, the Si substrate surface is formed a first plane and the Si normal feature has walls (sidewalls), normal with respect to the Si substrate surface, and a surface in a second plane, parallel to the first plane. Then, selectively forming a SiGe optical path overlying the Si normal feature includes forming a SiGe vertical optical path overlying the normal feature walls.

摘要翻译： 提供了SiGe垂直光路和用于选择性地形成用于IR光电检测的SiGe光路法线结构的方法。 该方法包括：形成Si衬底表面; 形成Si特征，相对于诸如沟槽，通孔或支柱的Si衬底表面是正常的; 并且选择性地形成覆盖Si正常特征的SiGe光路。 在一些方面，Si衬底表面形成第一平面，并且Si正常特征具有相对于Si衬底表面法线的壁（侧壁）和平行于第一平面的第二平面中的表面。 然后，选择性地形成覆盖Si正常特征的SiGe光路包括形成覆盖正常特征壁的SiGe垂直光路。

公开(公告)号：US20060189111A1

公开(公告)日：2006-08-24

申请号：US11060878

申请日：2005-02-18

申请人： Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas Tweet ,  Yoshi Ono ,  Sheng Hsu

发明人： Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas Tweet ,  Yoshi Ono ,  Sheng Hsu

IPC分类号： H01L21/44

CPC分类号： H01L27/127 ,  H01L27/1214 ,  H01L27/1266 ,  H01L29/7842 ,  H01L29/78621

摘要： A method of making CMOS devices on strained silicon on glass includes preparing a glass substrate, including forming a strained silicon layer on the glass substrate; forming a silicon oxide layer by plasma oxidation of the strained silicon layer; depositing a layer of doped polysilicon on the silicon oxide layer; forming a polysilicon gate; implanting ions to form a LDD structure; depositing and forming a spacer dielectric on the gate structure; implanting and activation ions to form source and drain structures; depositing a layer of metal film; annealing the layer of metal film to form salicide on the source, drain and gate structures; removing any unreacted metal film; depositing a layer of interlayer dielectric; and forming contact holes and metallizing.

摘要翻译： 在玻璃上的应变硅上制造CMOS器件的方法包括制备玻璃衬底，包括在玻璃衬底上形成应变硅层; 通过应变硅层的等离子体氧化形成氧化硅层; 在氧化硅层上沉积掺杂多晶硅层; 形成多晶硅栅极; 注入离子以形成LDD结构; 在栅极结构上沉积和形成间隔电介质; 植入和激活离子以形成源和漏结构; 沉积一层金属膜; 退火金属膜层，在源极，漏极和栅极结构上形成硅化物; 去除任何未反应的金属膜; 沉积层间电介质层; 并形成接触孔和金属化。

公开(公告)号：US20070298588A1

公开(公告)日：2007-12-27

申请号：US11891502

申请日：2007-08-10

申请人： Jer-Shen Maa ,  Jong-Jan Lee ,  Douglas Tweet ,  Sheng Hsu

发明人： Jer-Shen Maa ,  Jong-Jan Lee ,  Douglas Tweet ,  Sheng Hsu

IPC分类号： H01L21/301

CPC分类号： H01L21/26506 ,  H01L21/187 ,  H01L21/6835 ,  H01L2221/6835 ,  H01L2221/68368 ,  Y10S438/977

摘要： A method of fabricating a silicon-on-plastic layer via layer transfer includes depositing a layer of SiGe on a silicon substrate; depositing a layer of silicon; implanting splitting hydrogen ions into the silicon substrate; bonding a glass substrate to the silicon layer; splitting the wafer; removing the silicon layer and a portion of the SiGe layer; depositing a dielectric on the silicon side of the silicon-on-glass wafer; applying adhesive and bonding a plastic substrate to the silicon side of the silicon-on-glass wafer; removing the glass from the glass side of the bonded, silicon-on-glass wafer to form a silicon-on-plastic wafer; and completing a desired IC device on the silicon-on-plastic. Multi-level structure may be fabricated according to the method of the invention by repeating the last few steps of the method of the invention.

摘要翻译： 通过层转移制造硅塑料层的方法包括在硅衬底上沉积SiGe层; 沉积一层硅; 将氢离子注入到硅衬底中; 将玻璃基板结合到硅层; 分裂晶片; 去除所述硅层和所述SiGe层的一部分; 在玻璃上硅晶片的硅侧沉积电介质; 施加粘合剂并将塑料基板粘合到硅玻璃晶片的硅侧; 从接合的硅玻璃晶片的玻璃面上移除玻璃以形成硅 - 硅晶片; 并在塑料硅胶上完成所需的IC器件。 可以通过重复本发明方法的最后几个步骤，根据本发明的方法制造多层结构。

公开(公告)号：US20070099315A1

公开(公告)日：2007-05-03

申请号：US11353802

申请日：2006-02-13

申请人： Jer-Shen Maa ,  Jong-Jan Lee ,  Sheng Hsu ,  Douglas Tweet

发明人： Jer-Shen Maa ,  Jong-Jan Lee ,  Sheng Hsu ,  Douglas Tweet

IPC分类号： H01L21/00

CPC分类号： H01L31/1808 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02647 ,  H01L31/105 ,  Y02E10/50

摘要： A method of fabricating a germanium photo detector includes preparing a silicon substrate wafer and depositing and planarizing a silicon oxide layer on the silicon substrate. Contact holes are formed in the silicon oxide layer. An N+ epitaxial germanium layer is grown on the silicon oxide layer and in the contact holes. An N+ germanium layer is formed by ELO. The structure is smoothed and thinned. An intrinsic germanium layer is grown on the N+ epitaxial germanium layer. A P+ germanium layer is formed on the intrinsic germanium layer and a silicon oxide overcoat is deposited. A window is opened through the silicon oxide overcoat to the P+ germanium layer. A layer of conductive material is deposited on the silicon oxide overcoat and in the windows therein. The conductive material is etched to form individual sensing elements.

摘要翻译： 制造锗光电检测器的方法包括制备硅衬底晶片并在硅衬底上沉积并平面化氧化硅层。 在氧化硅层中形成接触孔。 在氧化硅层和接触孔中生长N +外延锗层。 N +锗层由ELO形成。 结构平滑和变薄。 内在锗层生长在N +外延锗层上。 在本征锗层上形成P +锗层，并沉积氧化硅外涂层。 通过氧化硅外涂层向P +锗层打开窗口。 一层导电材料沉积在氧化硅外涂层和其中的窗口中。 蚀刻导电材料以形成各个感测元件。

公开(公告)号：US20060246606A1

公开(公告)日：2006-11-02

申请号：US11120385

申请日：2005-05-02

申请人： Sheng Hsu ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas Tweet ,  Wei-Wei Zhuang

发明人： Sheng Hsu ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas Tweet ,  Wei-Wei Zhuang

IPC分类号： H01L21/8234

CPC分类号： H01L27/101 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1683

摘要： A method of fabricating resistor memory array includes preparing a silicon substrate; depositing a bottom electrode, a sacrificial layer, and a hard mask layer on a substrate P+ layer; masking, patterning and etching to remove, in a first direction, a portion of the hard mask, the sacrificial material, the bottom electrode; depositing a layer of silicon oxide; masking, patterning and etching to remove, in a second direction perpendicular to the first direction, a portion of the hard mask, the sacrificial material, the bottom electrode;, and over etching to an N+ layer and at least 100 nm of the silicon substrate; depositing of a layer of silicon oxide; etching to remove any remaining hard mask and any remaining sacrificial material; depositing a layer of CMR material; depositing a top electrode; applying photoresist, patterning the photoresist and etching the top electrode; and incorporating the memory array into an integrated circuit.

摘要翻译： 制造电阻器存储器阵列的方法包括制备硅衬底; 在衬底P +层上沉积底部电极，牺牲层和硬掩模层; 掩模，图案化和蚀刻以在第一方向上去除硬掩模，牺牲材料，底部电极的一部分; 沉积一层氧化硅; 掩模，图案化和蚀刻以在垂直于第一方向的第二方向上去除硬掩模，牺牲材料，底部电极的一部分，并且对N +层和至少100nm的硅衬底进行过蚀刻 ; 沉积一层氧化硅; 蚀刻以除去任何剩余的硬掩模和任何剩余的牺牲材料; 沉积一层CMR材料; 沉积顶部电极; 施加光致抗蚀剂，图案化光致抗蚀剂并蚀刻顶部电极; 并将存储器阵列并入集成电路中。

公开(公告)号：US20060113522A1

公开(公告)日：2006-06-01

申请号：US11327092

申请日：2006-01-06

申请人： Jong-Jan Lee ,  Sheng Hsu ,  Douglas Tweet ,  Jer-Shen Maa

发明人： Jong-Jan Lee ,  Sheng Hsu ,  Douglas Tweet ,  Jer-Shen Maa

IPC分类号： H01L29/06

CPC分类号： H01L29/785 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/78687

摘要： Disclosing is a strained silicon finFET device having a strained silicon fin channel in a double gate finFET structure. The disclosed finFET device is a double gate MOSFET consisting of a silicon fin channel controlled by a self-aligned double gate for suppressing short channel effect and enhancing drive current. The silicon fin channel of the disclosed finFET device is a strained silicon fin channel, comprising a strained silicon layer deposited on a seed fin having different lattice constant, for example, a silicon layer deposited on a silicon germanium seed fin, or a carbon doped silicon layer deposited on a silicon seed fin. The lattice mismatch between the silicon layer and the seed fin generates the strained silicon fin channel in the disclosed finFET device to improve hole and electron mobility enhancement, in addition to short channel effect reduction characteristic inherently in a finFET device.

摘要翻译： 公开了一种应变硅finFET器件，其具有双栅极finFET结构中的应变硅鳍通道。 所公开的finFET器件是由用于抑制短沟道效应和增强驱动电流的自对准双栅极控制的硅鳍通道组成的双栅极MOSFET。 所公开的finFET器件的硅鳍通道是应变硅鳍通道，包括沉积在具有不同晶格常数的种子鳍上的应变硅层，例如沉积在硅锗晶种鳍上的硅层或碳掺杂硅 层沉积在硅种子翅片上。 除了在finFET器件中固有的短沟道效应降低特性之外，硅层和种子鳍之间的晶格失配在所公开的finFET器件中产生应变硅鳍通道，以改善空穴和电子迁移率增强。

公开(公告)号：US20060099773A1

公开(公告)日：2006-05-11

申请号：US10985444

申请日：2004-11-10

申请人： Jer-Shen Maa ,  Jong-Jan Lee ,  Douglas Tweet ,  Sheng Hsu

发明人： Jer-Shen Maa ,  Jong-Jan Lee ,  Douglas Tweet ,  Sheng Hsu

IPC分类号： H01L21/30

CPC分类号： H01L21/76254 ,  H01L21/02052 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/0262

摘要： A method of fabricating a low defect germanium thin film includes preparing a silicon wafer for germanium deposition; forming a germanium film using a two-step CVD process, annealing the germanium thin film using a multiple cycle process; implanting hydrogen ions; depositing and smoothing a layer of tetraethylorthosilicate oxide (TEOS); preparing a counter wafer; bonding the germanium thin film to a counter wafer to form a bonded structure; annealing the bonded structure at a temperature of at least 375° C. to facilitate splitting of the bonded wafer; splitting the bonded structure to expose the germanium thin film; removing any remaining silicon from the germanium thin film surface along with a portion of the germanium thin film defect zone; and incorporating the low-defect germanium thin film into the desired end-product device.

摘要翻译： 制造低缺陷锗薄膜的方法包括制备用于锗沉积的硅晶片; 使用两步CVD工艺形成锗膜，使用多循环工艺退火锗薄膜; 植入氢离子; 沉积和平滑一层四乙基原硅酸盐氧化物（TEOS）; 准备一个反晶圆; 将锗薄膜结合到对置晶片上以形成结合结构; 在至少375℃的温度下对接合结构进行退火以促进键合晶片的分裂; 分离粘结结构以暴露锗薄膜; 从锗薄膜表面除去锗薄膜缺陷区的一部分剩余的硅; 并将低缺陷锗薄膜并入期望的最终产品装置中。

公开(公告)号：US20060019464A1

公开(公告)日：2006-01-26

申请号：US10894685

申请日：2004-07-20

申请人： Jer-Shen Maa ,  Jong-Jan Lee ,  Douglas Tweet ,  Sheng Hsu

发明人： Jer-Shen Maa ,  Jong-Jan Lee ,  Douglas Tweet ,  Sheng Hsu

IPC分类号： H01L21/30

CPC分类号： H01L21/76254 ,  Y10S438/977

摘要： A method of fabricating a silicon-on-glass layer via layer transfer includes depositing a layer of SiGe on a silicon substrate; relaxing the SiGe layer; depositing a layer of silicon on the relaxed SiGe layer; implanting hydrogen ions in a second hydrogen implantation step to facilitate splitting of the wafer; bonding a glass substrate to the strained silicon layer to form a composite wafer; splitting the composite wafer to provide a split wafer; and processing the split wafer to prepare it for subsequent device fabrication.

摘要翻译： 通过层转移制造硅 - 玻璃层的方法包括在硅衬底上沉积SiGe层; 放松SiGe层; 在松弛的SiGe层上沉积一层硅; 在第二氢注入步骤中注入氢离子以促进晶片的分裂; 将玻璃基板粘合到应变硅层以形成复合晶片; 分离复合晶片以提供分离晶片; 并处理分离晶片以准备其用于随后的器件制造。

公开(公告)号：US20050196894A1

公开(公告)日：2005-09-08

申请号：US10794158

申请日：2004-03-03

申请人： Jer-Shen Maa ,  Jong-Jan Lee ,  Douglas Tweet ,  Sheng Hsu

发明人： Jer-Shen Maa ,  Jong-Jan Lee ,  Douglas Tweet ,  Sheng Hsu

IPC分类号： H01L21/00 ,  H01L21/66 ,  H01L31/0352

CPC分类号： H01L31/035236 ,  B82Y10/00 ,  B82Y20/00

摘要： A 3D quantum dot optical path structure is provided, along with a method for selectively forming a 3D quantum dot optical path. The method comprises: forming a single crystal Si substrate with a surface; forming a Si feature in the substrate, such as a via, trench, or pillar; forming dots from a Ge or SiGe material overlying the Si feature; and, forming an optical path that includes the dots. In some aspects of the method, the Si feature has defect sites. For example, the Si feature may be formed with a miscut angle. As a result of the miscut angle, steps are formed in the Si feature plane. Then, the dots are formed in the Si feature steps. The miscut angle is in the range between 0.1 and 5 degrees, and the spacing between steps is in the range between 1 and 250 nanometers (nm).

摘要翻译： 提供了3D量子点光路结构以及用于选择性地形成3D量子点光路的方法。 该方法包括：用表面形成单晶Si衬底; 在衬底中形成Si特征，例如通孔，沟槽或柱; 从覆盖Si特征的Ge或SiGe材料形成点; 并且形成包括点的光路。 在该方法的某些方面，Si特征具有缺陷位点。 例如，Si特征可以形成为错误角度。 作为误差角的结果，在Si特征平面中形成台阶。 然后，在Si特征步骤中形成点。 误差角在0.1和5度之间的范围内，并且步骤之间的间隔在1和250纳米（nm）之间的范围内。

公开(公告)号：US20050153524A1

公开(公告)日：2005-07-14

申请号：US10755615

申请日：2004-01-12

申请人： Jer-shen Maa ,  Jong-Jan Lee ,  Douglas Tweet ,  David Evans ,  Allen Burmaster ,  Sheng Hsu

发明人： Jer-shen Maa ,  Jong-Jan Lee ,  Douglas Tweet ,  David Evans ,  Allen Burmaster ,  Sheng Hsu

IPC分类号： H01L21/762 ,  H01L21/02 ,  H01L21/30 ,  H01L21/46 ,  H01L27/12

CPC分类号： H01L21/76254

摘要： Transistors fabricated on SSOI (Strained Silicon On Insulator) substrate, which comprises a strained silicon layer disposed directly on an insulator layer, have enhanced device performance due to the strain-induced band modification of the strained silicon device channel and the limited silicon volume because of the insulator layer. The present invention discloses a SSOI substrate fabrication process comprising various novel approaches. One is the use of a thin relaxed SiGe layer as the strain-induced seed layer to facilitate integration and reduce processing cost. Another is the formation of split implant microcracks deep in the silicon substrate to reduce the number of threading dislocations reaching the strained silicon layer. And lastly is the two step annealing/thinning process for the strained silicon/SiGe multilayer film transfer without blister or flaking formation.

摘要翻译： 包含直接设置在绝缘体层上的应变硅层的SSOI（应变绝缘体硅）基板上制造的晶体管由于应变诱导的应变硅器件通道的带隙修改而增加了器件性能，并且由于 绝缘体层。 本发明公开了一种包括各种新方法的SSOI衬底制造工艺。 一个是使用薄的松弛SiGe层作为应变诱导的种子层，以促进整合并降低加工成本。 另一个是在硅衬底深部形成分裂的植入物微裂纹，以减少到达应变硅层的穿透位错的数量。 最后是对应变硅/ SiGe多层膜转移的两步退火/变薄处理，没有起泡或剥落形成。