Duplex chemical vapor deposition system and pulsed processing method using the same
    12.
    发明申请
    Duplex chemical vapor deposition system and pulsed processing method using the same 审中-公开
    双相化学气相沉积系统和使用其的脉冲处理方法

    公开(公告)号:US20060090702A1

    公开(公告)日:2006-05-04

    申请号:US11185689

    申请日:2005-07-21

    IPC分类号: C23C16/00

    CPC分类号: C23C16/409 C23C16/44

    摘要: Embodiments are provided of a duplex chemical vapor deposition (CVD) system and pulsed processing method using the same. The duplex CVD system may include first and second process chambers, one or more reactive sources, and reactive source suppliers that correspond to the reactive sources, respectively. The reactive source suppliers may include a first conduit portion connected to the respective reactive sources, a second conduit portion having one terminal connected to the first conduit portion and the other terminal connected to the first process chamber, and a third conduit portion having one terminal connected to the first conduit portion and the other terminal connected to the second process chamber.

    摘要翻译: 提供了双相化学气相沉积(CVD)系统和使用其的脉冲处理方法的实施例。 双相CVD系统可以分别包括对应于无源电源的第一和第二处理室,一个或多个无源电源和无源电源供应器。 反应源供应商可以包括连接到各个反应源的第一管道部分,具有连接到第一管道部分的一个端子和连接到第一处理室的另一个端子的第二管道部分,以及一个端子连接的第三管道部分 连接到第二处理室的第一管道部分和另一个端子。

    Ferroelectric capacitor having three-dimensional structure, nonvolatile memory device having the same and method of fabricating the same
    14.
    发明申请
    Ferroelectric capacitor having three-dimensional structure, nonvolatile memory device having the same and method of fabricating the same 失效
    具有三维结构的铁电电容器,具有相同的非易失性存储器件及其制造方法

    公开(公告)号:US20070051999A1

    公开(公告)日:2007-03-08

    申请号:US11515024

    申请日:2006-09-05

    IPC分类号: H01L29/94

    CPC分类号: H01L27/11502 H01L27/11507

    摘要: A ferroelectric capacitor having a three-dimensional structure, a nonvolatile memory device having the same, and a method of fabricating the same are provided. The ferroelectric capacitor may include a trench-type lower electrode, at least one layer formed around the lower electrode, a ferroelectric layer (PZT layer) formed on the lower electrode and the at least one layer and an upper electrode formed on the ferroelectric layer. The at least one layer may be at least one insulating interlayer and the at least one layer may also be at least one diffusion barrier layer. The at least one layer may be formed of an insulating material excluding SiO2 or may have a perovskite crystal structure excluding Pb.

    摘要翻译: 提供具有三维结构的铁电电容器,具有其的非易失性存储器件及其制造方法。 铁电电容器可以包括沟槽型下电极,形成在下电极周围的至少一层,形成在下电极和至少一层上的铁电层(PZT层)和形成在铁电层上的上电极。 所述至少一个层可以是至少一个绝缘中间层,并且所述至少一个层也可以是至少一个扩散阻挡层。 至少一层可以由除SiO 2之外的绝缘材料形成,或者可以具有不包括Pb的钙钛矿晶体结构。

    Non-volatile memory device and method of fabricating the same
    16.
    发明授权
    Non-volatile memory device and method of fabricating the same 有权
    非易失性存储器件及其制造方法

    公开(公告)号:US07910909B2

    公开(公告)日:2011-03-22

    申请号:US12232745

    申请日:2008-09-23

    IPC分类号: H01L45/00

    摘要: Provided are a non-volatile memory device that may be configured in a stacked structure and may be more easily highly integrated, and a method of fabricating the non-volatile memory device. At least one first electrode and at least one second electrode are provided. The at least one second electrode may cross the at least one first electrode. At least one data storage layer may be at an intersection between the at least one first electrode and the at least one second electrode. Any one of the at least one first electrode and the at least one second electrode may include at least one junction diode connected to the at least one data storage layer.

    摘要翻译: 提供了可以被配置为堆叠结构并且可以更容易地高度集成的非易失性存储器件,以及制造非易失性存储器件的方法。 提供至少一个第一电极和至少一个第二电极。 所述至少一个第二电极可以穿过所述至少一个第一电极。 至少一个数据存储层可以在至少一个第一电极和至少一个第二电极之间的交叉点处。 所述至少一个第一电极和所述至少一个第二电极中的任何一个可以包括连接到所述至少一个数据存储层的至少一个结二极管。

    Semiconductor device having a pair of fins and method of manufacturing the same
    17.
    发明授权
    Semiconductor device having a pair of fins and method of manufacturing the same 失效
    具有一对翅片的半导体器件及其制造方法

    公开(公告)号:US07833890B2

    公开(公告)日:2010-11-16

    申请号:US12457366

    申请日:2009-06-09

    IPC分类号: H01L21/4763

    摘要: Example embodiments relate to a semiconductor device and a method of manufacturing the same. A semiconductor device according to example embodiments may have reduced disturbances during reading operations and a reduced short channel effect. The semiconductor device may include a semiconductor substrate having a body and a pair of fins protruding from the body. Inner spacer insulating layers may be formed on an upper portion of an inner sidewall of the pair of fins so as to reduce the entrance to the region between the pair of fins. A gate electrode may cover a portion of the external sidewalls of the pair of fins and may extend across the inner spacer insulating layers so as to define a void between the pair of fins. Gate insulating layers may be interposed between the gate electrode and the pair of fins.

    摘要翻译: 示例性实施例涉及半导体器件及其制造方法。 根据示例实施例的半导体器件可以在读取操作期间具有减小的干扰,并且减少短信道效应。 半导体器件可以包括具有主体和从主体突出的一对鳍片的半导体衬底。 可以在一对翅片的内侧壁的上部形成内隔离层绝缘层,以减少对一对翅片之间的区域的入口。 栅极电极可以覆盖一对鳍片的外部侧壁的一部分,并且可以跨越内部间隔物绝缘层延伸,以便在一对鳍片之间限定空隙。 栅绝缘层可以插入在栅电极和一对鳍之间。

    NON-VOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME
    18.
    发明申请
    NON-VOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME 有权
    非易失性存储器件及其操作方法

    公开(公告)号:US20100027316A1

    公开(公告)日:2010-02-04

    申请号:US12465125

    申请日:2009-05-13

    IPC分类号: G11C11/00 G11C7/00

    CPC分类号: G11C8/14 G11C5/02 G11C5/025

    摘要: A non-volatile memory device having a stack structure, and a method of operating the non-volatile memory device In which the non-volatile memory device includes a plurality of variable resistors arranged in at least one layer. At least one layer selection bit line and a plurality of bit lines coupled to the plurality of the variable resistors are provided. A plurality of selection transistors coupled between the plurality of the bit lines and the plurality of the variable resistors are provided.

    摘要翻译: 具有堆叠结构的非易失性存储器件以及操作非易失性存储器件的方法其中非易失性存储器件包括布置在至少一层中的多个可变电阻器。 提供耦合到多个可变电阻器的至少一个层选择位线和多个位线。 提供耦合在多个位线和多个可变电阻器之间的多个选择晶体管。

    Semiconductor device having a pair of fins and method of manufacturing the same
    19.
    发明申请
    Semiconductor device having a pair of fins and method of manufacturing the same 失效
    具有一对翅片的半导体器件及其制造方法

    公开(公告)号:US20090253255A1

    公开(公告)日:2009-10-08

    申请号:US12457366

    申请日:2009-06-09

    IPC分类号: H01L21/28

    摘要: Example embodiments relate to a semiconductor device and a method of manufacturing the same. A semiconductor device according to example embodiments may have reduced disturbances during reading operations and a reduced short channel effect. The semiconductor device may include a semiconductor substrate having a body and a pair of fins protruding from the body. Inner spacer insulating layers may be formed on an upper portion of an inner sidewall of the pair of fins so as to reduce the entrance to the region between the pair of fins. A gate electrode may cover a portion of the external sidewalls of the pair of fins and may extend across the inner spacer insulating layers so as to define a void between the pair of fins. Gate insulating layers may be interposed between the gate electrode and the pair of fins.

    摘要翻译: 示例性实施例涉及半导体器件及其制造方法。 根据示例实施例的半导体器件可以在读取操作期间具有减小的干扰,并且减少短信道效应。 半导体器件可以包括具有主体和从主体突出的一对鳍片的半导体衬底。 可以在一对翅片的内侧壁的上部形成内隔离层绝缘层,以减少对一对翅片之间的区域的入口。 栅极电极可以覆盖一对鳍片的外部侧壁的一部分,并且可以跨越内部间隔物绝缘层延伸,以便在一对鳍片之间限定空隙。 栅绝缘层可以插入在栅电极和一对鳍之间。