公开(公告)号：US12207480B2

公开(公告)日：2025-01-21

申请号：US17899898

申请日：2022-08-31

Applicant: KIOXIA CORPORATION

Inventor： Tomoki Chiba ,  Daisaburo Takashima ,  Hidehiro Shiga

IPC: H10B63/00 ,  G11C11/16 ,  G11C13/00 ,  H10B61/00 ,  H10N70/00 ,  H10N70/20

Abstract: A variable resistance non-volatile memory includes a semiconductor substrate, a first electrode line extending in a first direction away from the semiconductor substrate, a second electrode line extending in the first direction parallel to the first electrode line, an insulating film between the first and second electrode lines, a variable resistance film formed on the first electrode line, a low electrical resistance layer formed on the variable resistance film and having a lower electrical resistance than the variable resistance film, a semiconductor film in contact with the low electrical resistance layer and the insulating film, and formed on opposite surfaces of the second electrode line, a gate insulator film extending in the first direction and in contact with the semiconductor film, and a voltage application electrode that extends in a second direction that crosses the first direction, and is in contact with the gate insulator film.

公开(公告)号：US12125545B2

公开(公告)日：2024-10-22

申请号：US17689182

申请日：2022-03-08

Applicant: Kioxia Corporation

Inventor： Reiko Sumi ,  Takashi Maeda ,  Hidehiro Shiga

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34 ,  G11C16/08

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/08

Abstract: A semiconductor memory device includes a driver that, in a write operation, applies a first voltage to a first select gate line, applies a second voltage lower than the first voltage to a second select gate line, applies a third voltage equal to or higher than the first voltage to a first dummy word line on an uppermost layer, applies a fourth voltage different from the third voltage and higher than the second voltage to a second dummy word line on an uppermost layer, applies a fifth voltage equal to or higher than the third voltage to a first dummy word line on a lowermost layer, and applies a sixth voltage different from the fifth voltage and equal to or higher than the fourth voltage to a second dummy word line on a lowermost layer.

公开(公告)号：US11972797B2

公开(公告)日：2024-04-30

申请号：US17679959

申请日：2022-02-24

Applicant: KIOXIA CORPORATION

Inventor： Hidehiro Shiga ,  Daisaburo Takashima

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0069

Abstract: A memory device includes a memory cell array including a select transistor and a plurality of memory cells connected in series, each memory cell including a cell transistor and a variable resistance layer connected in parallel. During a write operation, a voltage setting circuit is controlled to apply a first voltage to a selected word line and a second voltage to non-selected word lines. The time period for applying the first voltage to the selected word line starts later than the time period for applying the second voltage to the non-selected word lines and ends earlier than the time period for applying the second voltage to the non-selected word lines.

公开(公告)号：US11901011B2

公开(公告)日：2024-02-13

申请号：US17399548

申请日：2021-08-11

Applicant: Kioxia Corporation

Inventor： Kazutaka Ikegami ,  Hidehiro Shiga

IPC: G11C16/04 ,  G11C16/10 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

CPC classification number: G11C16/10 ,  G11C16/0483 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

Abstract: A semiconductor storage device includes a first word line, a second word line provided in the same layer with the first word line and configured to be controlled independently from the first word line, a plurality of memory pillars between the first word line and the second word line, each of the plurality of memory pillars including a first memory cell facing to the first word line and a second memory cell facing to the second word line, the plurality of memory pillars being arranged in a first direction and a second direction intersecting to the first direction and a control circuit. The control circuit is configured to perform a write operation to the second memory cell included in the plurality of memory pillars after performing a write operation to the first memory cell included in each of the plurality of memory pillars.

公开(公告)号：US11715527B2

公开(公告)日：2023-08-01

申请号：US17458059

申请日：2021-08-26

Applicant: KIOXIA CORPORATION

Inventor： Kazutaka Ikegami ,  Hidehiro Shiga ,  Takashi Maeda ,  Rieko Funatsuki ,  Takayuki Miyazaki

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/08 ,  G11C16/30 ,  G11C16/20 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/20 ,  G11C16/30 ,  H10B41/27 ,  H10B43/27

Abstract: A semiconductor storage device includes a semiconductor pillar, a first string having first memory cells connected in series, first word lines connected to the first memory cells, a second string having second memory cells connected in series, and second word lines connected to the second memory cells. Each of the first memory cells faces, and shares a channel in the semiconductor pillar with, one of the second memory cells. When reading data of the k-th first memory cell, a voltage of the first word line connected to the k-th first memory cell reaches a first voltage at a first timing, and a voltage of the second word line connected to at least one of the second memory cells other than the k-th second memory cell in the second string facing the k-th first memory cell reaches the first voltage at a second timing that is later than the first timing.

公开(公告)号：US11264106B2

公开(公告)日：2022-03-01

申请号：US17016580

申请日：2020-09-10

Applicant: Kioxia Corporation

Inventor： Hiroshi Maejima ,  Hidehiro Shiga ,  Masaki Kondo

IPC: G11C16/06 ,  G11C16/26 ,  H01L27/11556 ,  G11C16/04 ,  G11C16/34 ,  H01L27/11582 ,  G11C16/10

Abstract: A semiconductor memory device includes separate first and second word lines respectively facing first and second portions of a semiconductor and sandwiching the semiconductor; and first and second cell transistors respectively located in the first and second portions and respectively coupled to the first and second word lines. In a first operation, a first read is executed on the second cell transistor while a first voltage and a higher second voltage are being respectively applied to the first and second word lines. In a second operation, a second read is executed on the first cell transistor while a third voltage between the first and second voltages is being applied to the second word line.