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公开(公告)号：US12154615B2
公开(公告)日：2024-11-26
申请号：US18081265
申请日：2022-12-14
Applicant: Kioxia Corporation
Inventor： Takeshi Sugimoto , Takayuki Miyazaki
IPC: G11C11/4091 , G11C11/4096 , G11C11/4099
Abstract: A memory includes first cell layers respectively including first cells, and a second cell layer including dummy cells. A first wire is connected to the first cells arrayed in a first direction. A second wire is connected to the dummy cells arrayed in the first direction. A third wire is connected to the first cells and one of the dummy cells arrayed in a second direction. A fourth wire is connected to the third wires arrayed in a third direction. A first voltage is applied to a selected first wire when reading data from a selected first cell, and transmits a read data to a selected fourth wire connected to the selected first cell. A reference voltage is applied to a non-selected fourth wire. A second voltage is applied to a selected second wire provided with the dummy cell between the selected second wire and the non-selected fourth wire.
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公开(公告)号：US12119076B2
公开(公告)日：2024-10-15
申请号：US17679924
申请日：2022-02-24
Applicant: KIOXIA CORPORATION
Inventor： Takayuki Miyazaki , Yuki Ishizaki
CPC classification number: G11C7/065 , G11C7/1006 , G11C7/1057 , G11C7/106 , G11C7/12
Abstract: A semiconductor integrated circuit includes a plurality of sense amplifier units including a first group of sense amplifier units and a second group of sense amplifier units, a first data bus, a second data bus, a transfer circuit between the first data bus and the second data bus, and a data latch connected to the second data bus and to the first data bus through the transfer circuit and the second data bus. Each sense amplifier unit is connected to one of the bit lines. The first data bus is connected to each of the sense amplifier units in the first group. The second data bus is connected to each of the sense amplifier units in the second group. The transfer circuit controls the transfer of data between the first data bus and the second data bus in both directions.
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公开(公告)号：US11328770B2
公开(公告)日：2022-05-10
申请号：US17122063
申请日：2020-12-15
Applicant: Kioxia Corporation
Inventor： Takayuki Miyazaki
Abstract: A memory includes first-lines, second-lines, and memory cells. Third-lines are provided to respectively correspond to groups each comprising m (m≥2) lines of the first-lines. A first selector selects a certain one of the first-lines from the groups and to connect the selected first-lines to the third-lines corresponding to the groups. Fourth-lines correspond to the third-lines. A second selector selects one of the third-lines and to connect the fourth-line to the selected third-line. A third selector selects a certain one of the second-lines. A first driver applied a voltage to the fourth-line. A second driver is connected to the third selector. The first driver charges the third-line corresponding to the first-line selected from the groups via the fourth-line. The first and second selectors bring the selected first-line and the third-line corresponding the first-line to an electrically floating state. The second driver applies a voltage to the selected second-line.
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公开(公告)号：US11715527B2
公开(公告)日：2023-08-01
申请号：US17458059
申请日：2021-08-26
Applicant: KIOXIA CORPORATION
Inventor： Kazutaka Ikegami , Hidehiro Shiga , Takashi Maeda , Rieko Funatsuki , Takayuki Miyazaki
CPC classification number: G11C16/26 , G11C16/0483 , G11C16/08 , G11C16/20 , G11C16/30 , H10B41/27 , H10B43/27
Abstract: A semiconductor storage device includes a semiconductor pillar, a first string having first memory cells connected in series, first word lines connected to the first memory cells, a second string having second memory cells connected in series, and second word lines connected to the second memory cells. Each of the first memory cells faces, and shares a channel in the semiconductor pillar with, one of the second memory cells. When reading data of the k-th first memory cell, a voltage of the first word line connected to the k-th first memory cell reaches a first voltage at a first timing, and a voltage of the second word line connected to at least one of the second memory cells other than the k-th second memory cell in the second string facing the k-th first memory cell reaches the first voltage at a second timing that is later than the first timing.
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公开(公告)号：US20250104759A1
公开(公告)日：2025-03-27
申请号：US18819770
申请日：2024-08-29
Applicant: Kioxia Corporation
Inventor： Tsuneo Inaba , Takayuki Miyazaki , Shinji Miyano
IPC: G11C11/4074 , G11C11/4091 , G11C11/4094 , G11C11/4099
Abstract: A memory device includes a transistor, a capacitor, a plate line, and a bit line. The transistor includes an oxide semiconductor and includes a first end, a second end, and a gate. The capacitor includes a third end and a fourth end. The fourth end is coupled to the second end. The plate line is coupled to the third end. The bit line is coupled to the first end. A second voltage lower than a first voltage is applied to the plate line during a first period over which the first voltage is applied to the gate. A fourth voltage higher than the second voltage is applied to the plate line during at least a part of a second period over which a third voltage lower than the first voltage is applied to the gate.
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Patent Agency Ranking
公开(公告)号：US11081175B2
公开(公告)日：2021-08-03
申请号：US16943638
申请日：2020-07-30
Applicant: KIOXIA CORPORATION
Inventor： Yusuke Niki , Atsushi Kawasumi , Takayuki Miyazaki
Abstract: According to one embodiment, a device includes first lines transmitting a first signals; second lines receiving the first signals; and a first circuit including a first selector coupled to the first lines, a second selector coupled to the second lines, third lines and a fourth lines between the first and second selectors. Each of the third lines stores the second signals, each of the fourth lines stores the third signals. The first circuit counts a first number of second signals equivalent to the corresponding first signal; counts a second number of third signals equivalent to corresponding first signal of the first signals; and couples either the third or the fourth lines to the first and second lines via the first and second selectors, based on a result of comparison between the first and the second numbers.
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公开(公告)号：US11682455B2
公开(公告)日：2023-06-20
申请号：US17349095
申请日：2021-06-16
Applicant: Kioxia Corporation
Inventor： Takayuki Miyazaki
CPC classification number: G11C13/003 , G11C13/004 , G11C13/0069 , H10B63/30 , H10B63/80 , G11C2213/79
Abstract: A memory includes first lines arrayed along a surface of a substrate. Second lines are arrayed along the surface of the substrate either above or below the first lines and intersecting with the first lines. Resistance change memory cells are provided to correspond to intersection regions between the first lines and the second lines, respectively. First switching elements are arranged on a side of first ends of the first lines and transmitting a first voltage for writing or reading data to at least one memory cell among the memory cells. Second switching elements are arranged on a side of second ends of the first lines on an opposite side to the first ends and transmitting the first voltage to at least another one memory cell among the memory cells. The first switching elements and the second switching elements are connected to different ones of the first lines, respectively.
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公开(公告)号：US20230010266A1
公开(公告)日：2023-01-12
申请号：US17679924
申请日：2022-02-24
Applicant: KIOXIA CORPORATION
Inventor： Takayuki Miyazaki , Yuki Ishizaki
Abstract: A semiconductor integrated circuit includes a plurality of sense amplifier units including a first group of sense amplifier units and a second group of sense amplifier units, a first data bus, a second data bus, a transfer circuit between the first data bus and the second data bus, and a data latch connected to the second data bus and to the first data bus through the transfer circuit and the second data bus. Each sense amplifier unit is connected to one of the bit lines. The first data bus is connected to each of the sense amplifier units in the first group. The second data bus is connected to each of the sense amplifier units in the second group. The transfer circuit controls the transfer of data between the first data bus and the second data bus in both directions.
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公开(公告)号：US10949132B1
公开(公告)日：2021-03-16
申请号：US16803883
申请日：2020-02-27
Applicant: KIOXIA CORPORATION
Inventor： Reika Tanaka , Takayuki Miyazaki , Masumi Saitoh
Abstract: A storage device includes a substrate, first wirings arranged in a first direction and extending in a second direction, second wirings arranged in the second direction and extending in the first direction, resistance portions between the first and second wirings, third wirings between the second wirings and the substrate, arranged in the second direction and extending in a third direction, semiconductor portions each connected to second and third wirings, a fourth wiring extending in the second direction and facing the semiconductor portions, insulating portions between the semiconductor portions and the fourth wiring, and a contact connected to each first wiring. The semiconductor portions include a first portion and a second portion closer to the contact, and a length in the second direction of an insulating portion between the first portion and the fourth wiring is greater than that of another insulating portion between the second portion and the fourth wiring.
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公开(公告)号：US11942176B2
公开(公告)日：2024-03-26
申请号：US17475482
申请日：2021-09-15
Applicant: Kioxia Corporation
Inventor： Tomoya Sanuki , Xu Li , Masayuki Miura , Takayuki Miyazaki , Toshio Fujisawa , Hiroto Nakai , Hideko Mukaida , Mie Matsuo
CPC classification number: G11C5/14 , G11C16/30 , H02M3/1582 , H10B41/27 , H10B43/27
Abstract: A semiconductor memory device has a plastic package including an inductor, a first memory chip including a booster circuit that boosts a voltage from a first voltage to a second voltage using the inductor, and a second memory chip having a terminal supplied with the second voltage from the first memory chip.
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