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    SEMICONDUCTOR MEMORY DEVICE
    13.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20230074030A1

    公开(公告)日：2023-03-09

    申请号：US17984959

    申请日：2022-11-10

    Applicant: KIOXIA CORPORATION

    Inventor： Hiroshi MAEJIMA ,  Toshifumi HASHIMOTO ,  Takashi MAEDA ,  Masumi SAITOH ,  Tetsuaki UTSUMI

    IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00

    Abstract: A semiconductor memory device includes a memory chip. The memory chip includes a first region including a plurality of first memory cells and second memory cells, a second region different from the first region, a plurality of first word lines stacked apart from each other in a first direction in the first and second regions, a first pillar including a first semiconductor layer extending through the first word lines, and a first insulator layer provided between the first semiconductor layer and the first word lines, in the first region, the first memory cells being located at intersections of the first pillar with the first word lines, a first bonding pad in the second region, and a first transistor between the first word lines and the first bonding pad, and connected between one of the first word lines and the first bonding pad, in the second region.

    SEMICONDUCTOR MEMORY DEVICE
    14.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20220036951A1

    公开(公告)日：2022-02-03

    申请号：US17502573

    申请日：2021-10-15

    Applicant: KIOXIA CORPORATION

    Inventor： Hiroshi MAEJIMA

    IPC: G11C16/04 ,  G11C16/28 ,  G11C16/08 ,  G11C16/24 ,  G11C16/34 ,  G11C16/26

    Abstract: A semiconductor memory device includes a memory cell array having memory strings that include memory cells and first and second selection transistors. During a read operation, a controller applies a first voltage higher than ground to a source line, and a second voltage to a first and second selection gate lines that are connected to a selected memory string. The second voltage is also applied to the first selection gate lines connected to non-selected memory strings during a first period of the read operation. A third voltage higher than ground and lower than the second voltage is applied to the first selection gate lines connected to non-selected memory strings during a second period of the read operation subsequent to the first period.

    SEMICONDUCTOR MEMORY DEVICE
    15.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210158876A1

    公开(公告)日：2021-05-27

    申请号：US17016580

    申请日：2020-09-10

    Applicant: Kioxia Corporation

    Inventor： Hiroshi MAEJIMA ,  Hidehiro SHIGA ,  Masaki KONDO

    IPC: G11C16/26 ,  H01L27/11556 ,  H01L27/11582 ,  G11C16/04 ,  G11C16/34

    Abstract: A semiconductor memory device includes separate first and second word lines respectively facing first and second portions of a semiconductor and sandwiching the semiconductor; and first and second cell transistors respectively located in the first and second portions and respectively coupled to the first and second word lines. In a first operation, a first read is executed on the second cell transistor while a first voltage and a higher second voltage are being respectively applied to the first and second word lines. In a second operation, a second read is executed on the first cell transistor while a third voltage between the first and second voltages is being applied to the second word line.

    SEMICONDUCTOR MEMORY DEVICE
    16.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20200335513A1

    公开(公告)日：2020-10-22

    申请号：US16795763

    申请日：2020-02-20

    Applicant: KIOXIA CORPORATION

    Inventor： Naohito MOROZUMI ,  Hiroshi MAEJIMA

    IPC: H01L27/11573 ,  H01L27/11565 ,  H01L27/1157 ,  G11C16/16 ,  G11C16/26 ,  G11C7/06 ,  G11C16/08 ,  G11C16/24 ,  H01L23/00

    Abstract: A semiconductor memory device according to an embodiment includes a memory chip and a circuit chip. The memory chip includes first and second joint metals. The circuit chip includes first and second sense amplifiers, and third and fourth joint metals facing the first and second joint metals, respectively. The first sense amplifier includes first and second active regions. The first active region includes a first transistor coupled between the third joint metal and the second active region. The second amplifier includes third and fourth active region. The third active region includes a second transistor coupled between the fourth joint metal and the fourth active region. The third and fourth joint metals overlap the first and third active regions, respectively.

    SEMICONDUCTOR STORAGE DEVICE
    18.
    发明公开
    SEMICONDUCTOR STORAGE DEVICE 审中-公开

    公开(公告)号：US20240296888A1

    公开(公告)日：2024-09-05

    申请号：US18653785

    申请日：2024-05-02

    Applicant: Kioxia Corporation

    Inventor： Hiroshi MAEJIMA

    IPC: G11C16/04 ,  G11C5/06 ,  G11C7/06 ,  G11C16/08 ,  G11C16/26 ,  H01L23/522 ,  H01L23/528 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

    CPC classification number: G11C16/0483 ,  G11C5/063 ,  G11C7/06 ,  G11C16/08 ,  G11C16/26 ,  H01L23/5226 ,  H01L23/528 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

    Abstract: A semiconductor storage device includes word lines extending in first and second directions, and separated from each other in a third direction, sense amplifier circuits that partially overlap the word lines in the third direction, memory strings intersecting the word lines and extending in the third direction, memory-side bit lines extending in the first direction, separated from each other in the second direction, and including first and second adjacent memory-side bit lines, circuit-side bit lines between the word lines and the sense amplifier circuits and partially overlapping the respective memory-side bit lines in the third direction, and contact plugs extending in the third direction and respectively connecting the memory-side bit lines and the circuit-side bit lines. The contact plugs include first and second contract plugs that are electrically connected to the first and second memory-side bit lines, respectively, and are not aligned along the first or second direction.

    SEMICONDUCTOR STORAGE DEVICE AND CONTROLLER
    20.
    发明申请
    SEMICONDUCTOR STORAGE DEVICE AND CONTROLLER 有权

    公开(公告)号：US20230032500A1

    公开(公告)日：2023-02-02

    申请号：US17962302

    申请日：2022-10-07

    Applicant: KIOXIA CORPORATION

    Inventor： Hiroshi MAEJIMA

    IPC: G11C16/10 ,  G11C16/16 ,  G06F12/02 ,  G11C16/04 ,  G11C16/34 ,  G11C11/56 ,  G06F3/06

    Abstract: A semiconductor storage device includes memory cells, select transistors, memory strings, first and second blocks, word lines, and select gate lines. In the memory string, the current paths of plural memory cells are connected in series. When data are written in a first block, after a select gate line connected to the gate of a select transistor of one of the memory strings in the first block is selected, the data are sequentially written in the memory cells in the memory string connected to the selected select gate line. When data are written in the second block, after a word line connected to the control gates of memory cells of different memory strings in the second block is selected, the data are sequentially written in the memory cells of the different memory strings in the second block which have their control gates connected to the selected word line.

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